1899 lines
60 KiB
Plaintext
Executable File
1899 lines
60 KiB
Plaintext
Executable File
HARDWARE REFERENCE
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Version 2.10
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NOTE: The data in this manual is provided for information only. You are strongly advised not to make
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direct access to any of the hardware since this may conflict with access made by EPOC. To guarantee
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future compatibility, hardware access should only be made via the apropriate operating system calls.
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February 3, 1995
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(C) Copyright Psion PLC 1990-95
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All rights reserved. This manual and the programs referred to herein are copyrighted works of Psion
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PLC, London, England. Reproduction in whole or in part, including utilization in machines capable of
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reproduction or retrieval, without express written permission of Psion PLC, is prohibited. Reverse
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engineering is also prohibited.
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The information in this document is subject to change without notice.
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Psion and the Psion logo are registered trademarks, and Psion, Psion MC, Psion HC, Psion Series 3,
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Psion Series 3a and Psion Workabout are trademarks of Psion PLC.
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IBM, IBM XT and IBM AT are registered trademarks of International Business Machines Corp.
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Microsoft and MS-DOS are registered trademarks of Microsoft Corporation. Apple and Macintosh are
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registered trademarks of Apple Computer Inc. VAX and VMS are registered trademarks of Digital
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Equipment Corporation. 80C86, 8088, 8288, 8259 and SLD are registered trademarks of Intel
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Corporation. V30 and V30H are registered trademarks of NEC Corporation. Brief is a registered
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trademark of Underware Inc. Psion PLC acknowledges that some other names referred to are registered
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trademarks.
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SE ee a ae es
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Contents
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—_— eee
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T ‘The. Principali Chip Seti. iivediodscesscsen ec ennertete teste teak iotaseveieee hs Beckcecek 1
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PRG Ma ixs coe coer er iasares cud cthtenteranadlanss tak peeen aed scdavaei wis APU cos ne CIS al edits 2
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BuUSSCONtCONE Rs «sas sewaschsv ae sicnne sescaueenpecy mrs roe Fe Sees set ee ee 2
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BUSS CONVENED .0:cs<sveccescuskanstvnced sa duadeanes<dugndined olen Dt eee, ead 2
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DTS Fore eas scc stone Sencancbiesa ave gnsaeesenacstaataapivesstuatiae biee. hem eieiiee eet he eee 2
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EC DICOntrollenh scc.csnstet eran ineactoesnt cuss ct eet ea re ee et es 3
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MEMOry CecOdiNGh vcrvaceuteats sce seeietessne tuekte sr biat terre ee rere tees 3
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iOrdecodingy wee. 5. Aoi te Pesan eS Me ee ee eee 4
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Intenruptecomtroller encase ce tetas cote ate ee cae sete este 4
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WatehGogMtimert cwicsrcni acs tire Meats asascoa aves settee ee ome masicc cs 4
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Address and 1/0 protection...........ccccceccseccescsccececcsstoneesctesecssacsceceecceces 4
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ASI G2 tate, unt mcasoedy, sore es stevbaonee he ea eesieoeaes Se 4
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System clock Oscillator ..............ceseseeceeceuccesssuccessescecencessteesssausaucevence 5
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OG OTINGOMU Olas eine ite t.scsere szunesete rats Letuu dtc padre ecore tetr eae see bes 5
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SIBO serial protocol COMtFONER:<:iccicdisissscescnestaesaiciee eae bee Nee 5
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SIBO serial protocol slave.............ssssscsvccssccecssccreccaveceuceestsvececcsseccesencs 5
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Keyboard: interlace ix. cectie.csscceerics aces bee ce sie vec sunne tie Wureek a aoc eee hev uns 5
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BulZZenMteM aCe sees sates teases Sots cccbc erty ann setea ances comma se auwhuctaatt ts Mec oic 5
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NIMPOBRERARGM ssssauonepasecteartuanstct sa cestvonda ravens saineaay ox vad olveuiesi Puan. Miule idee 5
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PENG ea tives een cuth A Saneet bavaecsiee phe boner enwats viegtdauseevnadeeacanh iaaaimbest Seeramemenadetted 6
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Increased Memory addressing............ssssccscssecesesesconssscccuscecauscscnesseeses 6
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Incréased.processomspeed-.<.isc:. s::.c0ss0ssdaereceents PR ee 6
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Improved Pack performance with hardware wait ...........cc-sssssccsssccscesces 6
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Addition of hardware 32 bit RTC...........cccssssecceeccsssccssceccesseecesesescesueces 6
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Improved sound facilities ...............ccccssccssecescesccreconsceuccescescesesccecensens 7
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Switch on via the membrane key pads ...........scccsscccsescecescesccecceeseusnecess 7
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Facility to address two ROM SIteS ..............ccccsesccssecccssecescctscsesssecseesees 7
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AUG nal ERE wicwasaecceessnsevencsseaulovis Sesienwets vuncas vay nmpdessvduaiiees ce eekeux och 7
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WTPROVEO GIO Y SCAIG vite cexdsctccdeSeuninan biavnsevietrc teu toeecs coigs auntersiWeeeneeats 7
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Triple Serial Control and Data Registers............sscsccsssceseccosscesccesscceseucss 7
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Contiguous video MEMOSry MAP.........cccccsccesccscocssccnscosseecesscesseavenseccoess 7
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Expansion support in SSD Slots ............cscccseccescceesssecssccncccasscesscenseuseus 7
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Altered Interrupt allocation ...............cssscossscoesecnsscccusccsescarssensecsseeereescs 8
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POU SUDSV STON act zesiantcbianec® tans duntataddweacuaausivedea’ saatune sould poke de AOL Sos eas 8
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Thexstand Dy State’. csadeizs. saieslovivescasgus cases sonveceadseddessueteitevee alee gteslease., 8
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The DaCKUP:State efits; ociedccedesuenedeclaed ec sveeseecetorceeses avec ss Gavi bedoveeeieosetoes 8
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WAS WOE SCALE adaisinrwesiesrens Saxe t snc vaxcuaee doxapadien viewadviveeueocasnets oa vuavedeatieiaarect 8
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The Operating State .........cccccscssceccsececsccecceccecsscusececascesesecsccececuscacevencs 8
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MOG 1 /SUDDIY Saterccdausesgesasmunecuwecectoutroe dst evasiunnadisnndtitaccdowsy pectietvah lees 8
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WEC2 SUDDIY srtserueniddievanuss ens msvadantaasutonasameniaucses RAwapecdintenl sohen eee 9
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MCCS: SUI cai osuia cise apiveatoos aug eels eanaratnu supa ru caiaewe id ioe licen cots a uactiadiaasloun Mee 9
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VGC4ISUDDIY ccacsns vedas egos cdeccdeead< oa seee vasa Gov dexisibetasecsaulesdeeeveriweteessl eens ane 9
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MGCS SUPPLY cai svesdiaieah les letaduaca ss bores cuba veins cola doucited dccesaberiaboaebeearbext 9
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VEO 1 SUPDIY cc...sadusiciedss vasdeveves ces pales favaiee ede ve anne seseuaincosnaterhc doveReboae 9
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Vee 2PSUPDIY seas iceutivaessscectauis 4 oste succes vereceunnasedcoaceseansieiwenges iene dunsesesext 9
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VINSUPDIY Seed beniacis cevete ses cavesignetaswsce Zeb vdshidvesiadedoideens eae lok dose nowend wate sats 9
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2 The SIBO Serial Protocol................cccccccecscsecccscacsccscecenssssececesccscecscucsacersccceacce 11
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Flardware Interface: .c.c.eiecdisveaeincs Sch ola Sook ceeune eSeiu cen. Svecdedos ou adiooasse we btiee: 11
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ClOCK LING vise cescousnacaewsiSeatavcecucd goneeecade ae ab cdiade recente oll ates dae 11
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Data lin @ ict cinteoranet lest euecsuescutesee cue wcbetedsweceoaes cut oehessewt ch cies Reuehcti oles 12
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The Physicalilayen: vvs.sdsdcecaosvevcnduenssagevacessssceudsavaskiwenseycoelics covudesoodecbecse ste 12
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Frame! StLUCtUlG oc oc scajet sn sad ice vaveudascessdsceuesahaavavekcsaidseetwedavecsseccks dose nebecs 12
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INGHER AIM Osc: orcs cccccs seccudis veeece cashes tuk aoadaee cea c ithe suet bbe ee ecutnptlesoat 13
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GONtrOMNtrame@sacs Seer ccevcceces sie ccckcoece se cea eee eee Se cece steer see ane Bocas 13
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HARDWARE REFERENCE
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DatarOQutputs Rrames.ieas ccd eve atadenseadebesevscceehanenntcus vonseucdovecsedsenetocaaes’ 13
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Datagnputghrame ns cic. czars ct ecs.ssdectaieonsess beat eeeessoses fae aba ares oe 13
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Datalinesdirection vcs sscsscesceenscccecMevcscesscccssoehs cveeupesasccscbivas suber enceyiuieiee 14
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TL NEMBFANSPOFAV SNE Feiss is vsencecvcsCona seals veveveoneaveeveed den stsvarceoeus saves dentes os beats 14
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SlaVemSelOCtMOde:. si.idecsvisss eaisccsecde gssavedesgesivens seiaecaseedscss Ghocetwberessassees 15
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SlAVELCONTOl MOMS eke ees Hoek cas caaecnneubaese deeds eoecoo pessoa cacasdee s5eee ieee dane 15
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MMI Ofesec cee scotteccsuu instore cvewesecundt pe caceateet sewn seu bol waves uUeeces cveh tame eeeree et 17
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STATS eis ossccectvvetseadsess due dias savuseascaslabi gubieinees shapieadoctec accent eee 17
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3 The: SIBO..Expansion Poms’... <.5c.cccscovcssascsacusedsvoucdecsacges ccdeeueeceseeemaneco tess eraae sess 19
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Extended internal expansion .............cscscccsccerscseceecencocsseveereseccssseseucncesence 19
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PAYSICAlCONMCCtOl an. ccsccessse.ccesece .setassee ss scesee sos nonvers ce chaclwanseuteteie ree 19
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SiGHal’ASNIOM 6: Fe. 2 see deescessassdecesc tus ccusesta asa vagaesenadicdevdeseneoseoM ol mites ee 20
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Din Ctal/O OM risct cecwaseiisen comeveddaa casasessoaceves oe de ies ce agea cain nea Wek atlobeeibas eet eubece 20
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The S|IBO’serialschannels. s. cvcvscesenveviess choiccwos hese cela sdatawcens necasuaieges eeees 22
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POWEFESUDDILESS. cet cous sccscug eae cns te oscsiien seauec totus denies hen hence iiebe teat betconcds 22
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Reduced external Expansion ..........cscsccscoscecsccscesceccueucuvevenseeteseceesencneseceees 22
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Physical’ COnnMeCton eis sczeesclcse.ccisececs saceaeveswesce rete oueies deck ceeenns een a eons 22
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SIGHAal GETIMUOM: .f2-sserss ease cucecsewssee es sea vouehenene sdecei bdesgsesegeSeoes cacstoyoes 22
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Example expansion devices ...........ccsccsecsecsccectstetstecessessesescueesescucneeseesens 23
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Extended expansion example one - 8 bit read/write port..........ccscvessseeees 23
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Extended expansion example two - 16 channel ADC ............ccccsesecceeeess 23
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Reduced expansion example three - TTL RS232 based interface............. 24
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CHAPTER 1
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THE PRINCIPAL CHIP SET
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Current SIBO products in the MC, HC and Series 3 range are based on the same three principal chips.
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These are the V30H (a 8086 compatible processor) and two Psion custom chips known as AS/CI and
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ASIC2. Later SIBO products including the Series 3a have these three devices integrated into a single
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Psion custom chip known as ASIC9.
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The V30H is an enhanced 16 bit CMOS version of the 8088 found in the original IBM PC. It is software
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compatible with the 8088. The V30H is a fully static design, which means that all the internal storage
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elements i.e. its registers are made from static rather than dynamic storage elements. This means there is
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no minimum clock speed required to refresh the storage elements and the system clock can be Stopped at
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any time with no loss of internal state. This technique is used extensively in the SIBO architecture to save
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power while the processor is idle i.e. waiting for an event.
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ASICI and ASIC2 are Psion specific gate arrays based on a one micron full CMOS process. They are
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described in more detail in the next sections.
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Figure 1 shows a simplified block diagram of the SIBO architecture showing the principal three chips.
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ADCO-15) MD¢0-79
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AC1E-199 MACO-1B)
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& MICROPHONE
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Ss (
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V_ SPEAKER
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AUDIO AMP GND
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SYSTEM CONTROL
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AD(O-7)
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cOLCO-11) OLCO-11>
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ROWCO-7 9 ROWCO-7)
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SYSTEM
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OSCILATOR a
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Figure 1.
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HARDWARE REFERENCE
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A en ree]
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ASIC1
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ASIC1 contains approximately 4300 gates, implemented on a Hitachi one micron CMOS gate array in a
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100 pin quad flat pack package.
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ASIC1 is the main system controller for the SIBO architecture. It connects directly to the 80C86 in
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maximum mode controlling all bus cycles to and from the processor. This configuration effectively forms
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a micro-controller like device that executes 8086 instruction codes. ASIC1 is made up of a number of
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functional blocks described below.
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The bus controller converts the encoded bus cycle requests (present on SO-S2) from the processor into the
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appropriate memory and I/O control signals. The bus controller is similar to the Intel 8288 device but
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with several enhancements, these are:-
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1) Clock stopping on the HALT instruction. Whenever a HALT instruction is issued by the
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processor the clock line to the processor is stopped and held low until either an NMI or an
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interrupt is asserted.
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2) Bus arbitration during video refresh cycles. Bus cycles to the video RAM segment are
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delayed while a video refresh is in progress.
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3) Memory write and I/O blocking. Memory writes outside pre-programmed segments and all
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1/O instructions can be blocked by the bus controller. See following sections on address and
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1/O protection.
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Memory access to the 8-bit bus are converted to 16 bit accesses by the bus converter. This means that the
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80C86 can access memory on the 8-bit bus as if it were 16-bits wide.
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ASICI can operate in two modes dependant on a strapping pin: 16 bit memory mode or 8 bit memory
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mode. 16 bit mode allows higher processor clock speeds for a given memory access time but requires a
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full 16 bit bus and hence 16 bit wide memory. 8 bit mode requires higher speed memory for a given
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processor clock speed but only requires an 8 bit bus and 8 bit wide memory. In all MC's ASIC] operates
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in 16 bit mode, while the HC operates in 8 bit mode.
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In 16 bit mode all the system memory except for the video RAM is connected to the 16 bit bus. The
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video RAM is defined as a 32K segment of RAM between B8000 and C0000 hex. Any memory access to
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this segment is converted to two 8 bit memory accesses on the 8 bit bus by the bus conversion logic.
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These accesses may delay the 80C86 by stopping the clock to allow time for the two accesses or to allow
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a video refresh access to take place.
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In 8 bit mode all system memory is connected to the 8 bit bus so all memory accesses need to be
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converted. This means that memory needs to be faster for a given clock speed than in 16 bit mode,
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because two memory accesses need to be "squeezed" into one bus cycle. The video RAM is just part of
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the system RAM and is of variable size dependent on the LCD screen size with a base address of 400
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hex.
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Timer
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A general 16 bit count down timer is provided by ASIC]. When the system is not in the standby state i.e.
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the processor is running, the clock source can be programmed to be either a fast (512 KHZ) clock or a
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slow (32 Hz) clock. Any 16 bit value can be written into the timer at any time. This value will then be
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decremented on the next rising edge of the clock. The current value in the timer can be read at any time.
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When the value in the timer reaches zero an interrupt is generated. When the system is in the standby
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state the timer is clocked from the 32 Hz real time clock oscillator in AS/C3 so that time can be kept
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while the processor is powered down.
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The timer can operate in two modes controlled by a programmable bit, free running mode or prescale
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mode. In free running mode, when the timer decrements to zero an interrupt is generated and the counter
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just wraps around to -1 (FFFF). In prescale mode when the interrupt is generated the original value
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written to the timer is re-loaded automatically, this allows the interrupt to become a rate programmable
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pulse stream. This pulse stream is also an output from ASICI.
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1 THE PRINCIPAL CHIP SET
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The LCD controller provides all the necessary ti
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of up to 640 by 400 dots in size.
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The data is output on up to eight signals. Each data signal outputs serial data that is synchronous with the
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dot clock. The data is a continuous bit stream formed from serialised data taken from the video refresh
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RAM. The data is serialised so that the first pixel in a line is bit 0 in the corresponding byte of the video
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RAM, this means the video RAM can be accessed in words i.e 16 bits wide.
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The timing and data signals are controlled by a number of programmable registers which allow the
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following parameters to be set:
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1) Lime length - the number of dots in the line.
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2) Frame length - the total number of dots in the screen.
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3) Refresh rate - sets the refresh rate. This should be calculated from the system clock speed
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and the screen size to give a refresh rate of approximately 70 frames per second.
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4) AC drive rate - sets the frequency of the AC drive signal to the LCD module as a function
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of the line rate. This should be calculated to be approximately 300 Hz.
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5) Display mode - four different display modes are supported these are: single screen refreshed
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from video page one; single screen refreshed from video page two; single screen refreshed
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from video page one and two giving a two bit grey scale; and double screen refreshed from
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video page one and two.
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8 bit memory decoding allows for different sized physical memory devices to be connected to the logical
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memory slots. Three memory device size options are supported allowing for 32K x 8, 128K x 8 and
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512K x 8 devices to be addressed. These options are selected by two programmable bits, MSELO and
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MSELI.
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The following table summarises the memory device size options:-
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MSEL1 MSELO Device size
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The following table summarises the memory decoding performed by ASICI:-
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00000 - IFFFF
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8 Bit slot 0
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00000 - O7FFF 00000 - 7FFFF
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8 Bit slot 1 08000 - OFFFF | 20000 - 3FFFF 80000 - FFFFF
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8 Bit slot 2 10000 - 17FFF | 40000 - SFFFF -
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8 Bit slot 3 18000 - 1FFFF | 60000 - 7FFFF -
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8 Bit slot 4 20000 - BFFFF | 80000 - BFFFF 80000 - BFFFF
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8 Bit slot 5 C0000 - FFFFF} C0000 - FFFFF C0000 - FFFFF
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B8000 - BFFFF
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00000 - B7FFF + C0000 - FFFFF
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16 Bit 8 Bit slot 1
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16 Bit 16 Bit slot
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HARDWARE REFERENCE
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0300 - FFFF Not used
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0200 - 02FF Expansion port 2
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0100 - O1FF Expansion port 1
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0090 - OOFF Not used
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0080 - 008F I/O space in ASIC2
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0020 - 007F Not used
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0000 - 001F Internal I/O in ASICI
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The interrupt controller in AS/CJ prioritises eight interrupt request lines to generate a single interrupt
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request to the processor. When and if the processor executes an interrupt acknowledge cycle, the
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interrupt controller places the correct vector on the bus.
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The interrupt controller is similar to the Intel 8259 device, however, the following restrictions apply;
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there is no provision for daisy-chaining additional interrupt controllers, level triggered mode only is
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supported and the interrupt vector base is fixed at 78 hex.
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The 8 interrupts are defined internally in ASJCI as follows:
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78
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Tick interrupt at 2 or 32 Hz
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External interrupt usually connected to mains detect bit
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External interrupt from expansion port one
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External interrupt from expansion port two
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External interrupt from ASIC2
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SLD sound receive interrupt
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SLD sound transmit interrupt
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Watchdog timer —S<—h 3 vhUhm™m™C™t~—O—OCOCC—O
|
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The watch dog timer is a two bit counter which counts up at a rate of 4 Hz. If the count reaches three a
|
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NMI is generated. The counter can be reset by a write to an I/O location inside ASJC1. Normally the
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counter is reset on every tick by the interrupt service routine. The NMI will be produced after 24 ticks
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have passed with no reset, this equates to 0.75 of a second with interrupts disabled.
|
||
|
||
|
||
The range is set by writing the upper and a lower segment bounds for the given range to two internal 16
|
||
bit registers in ASIC].
|
||
|
||
|
||
Protected mode is switched on and off by writing to or reading from a special I/O location in ASICI.
|
||
|
||
|
||
eA
|
||
ASIC2
|
||
|
||
|
||
ASIC2 contains approximately 2200 gates, implemented on a Hitachi one micron CMOS gate array in an
|
||
80-pin quad flat pack package.
|
||
|
||
|
||
ASIC2 contains the system clock oscillator, controls switching between the standby and operating states,
|
||
and provides an interface to the power supply, keyboard, buzzer, SSDs and expansion ports. ASIC2
|
||
consists of the following functional blocks:
|
||
|
||
|
||
1 THE PRINCIPAL CHIP SET
|
||
ee EEEeEEEFSFSFSSSSSSSSSSSSSSSSSSMMsFsFeFesesesesesMsSSSFSsFsFse
|
||
|
||
|
||
An on-chip oscillator cell connected to an external crystal generates the main system clock in the
|
||
operating state. The system clock frequency is divided down to provide clocks for the serial channels, the
|
||
SLD bus interface and for RS232 communication. The oscillator is disabled in the standby and battery
|
||
|
||
|
||
backup states to conserve power.
|
||
|
||
|
||
ASIC2 controls switching between the standby and operating states. AS/C2 puts the system into the
|
||
operating state when: the keyboard "on" signal is asserted; the system "reset" signal is generated; an
|
||
expansion device requests service; an external controller initiates a "high speed link" or the AS/C/ timer
|
||
reaches zero.
|
||
|
||
|
||
Switching from the operating state to the standby state is software controlled. When an "enter standby"
|
||
command is written to ASIC2 it shuts down the power supply via the serial interface and puts the system
|
||
into the standby state.
|
||
|
||
|
||
ASIC2 contains an 8-channel SIBO serial protocol controller which provides an interface to the power
|
||
supply, the SSDs, the expansion ports and the high speed link. Channel assignments are:
|
||
|
||
|
||
Power supply (ASIC3)
|
||
|
||
|
||
SSDs
|
||
Expansion ports
|
||
High speed link
|
||
|
||
|
||
Serial clocks 5 & 6 may be set free running at 1.536Mhz, this frequency may be divided down by devices
|
||
connected to the expansion ports to provide baud rates for RS232 communication.
|
||
|
||
|
||
To maximise the data transfer rate, a "controller busy" signal is generated by ASIC2 during a data
|
||
transfer. This signal is connected to the processor TEST pin.
|
||
|
||
|
||
For further details refer to "The SIBO serial protocol” chapter of this manual.
|
||
|
||
|
||
is used for the "high speed link" to receive data transmitted by an external
|
||
controller. An interrupt is generated when a frame is received.
|
||
|
||
|
||
ASIC2 provides an interface to a matrix keyboard of up to 192 keys, made up from 16 rows by 12
|
||
columns. During a keyboard scan the columns are each driven high in tum by ASIC2 and the row
|
||
information is read from the keyboard row register. Normally the row buffer is 8 bits wide which gives a
|
||
matrix of 8 x 12 i.e. 96 keys.
|
||
|
||
|
||
A piezo electric buzzer element can be connected directly to AS/C2. The buzzer can be driven at high or
|
||
low volume, and either directly by toggling an ASIC2 register bit or by the overflow bit from the ASIC!
|
||
timer.
|
||
|
||
|
||
NMI g
|
||
|
||
|
||
ASIC2 controls the generation of an NMI which is passed onto the processor via ASIC. This NMI can
|
||
be generated from a number of sources, these are, power fail conditions and SSD or expansion port door
|
||
micro-switches. When the main power supply voltage (Vsup) falls to a level insufficient to power the
|
||
system ASIC3 signals ASIC2 and a power fail NMI is generated. When an expansion device is removed
|
||
or inserted, or if an SSD is removed or inserted micro-switches connected to ASIC2 generate the
|
||
appropriate NMI. The source of the NMI is identified by reading a register in ASIC2.
|
||
|
||
|
||
HARDWARE REFERENCE
|
||
|
||
|
||
SS SSS ee ee |
|
||
ASICS
|
||
|
||
|
||
The Series 3a differs from the above description in that the V30H and all the functions in ASIC] and
|
||
ASIC2 have been integrated into a single custom device known as ASIC9. This has allowed faster
|
||
processing speeds and lower power consumption to be achieved. In addition a number of enhancements
|
||
and alterations have been made to the SIBO architecture listed below.
|
||
|
||
|
||
. This allows larger mas
|
||
ROM's and RAM's to be addressed. This is done by implementing bank switching in ASIC9 which will
|
||
be similar to EMS on PC's.
|
||
|
||
|
||
Each bank is 64 KBytes in size and is selected by writing into one of four page registers, two to select a
|
||
RAM address and two to select ROM addresses. These page registers are called PSELO to PSEL3
|
||
respectfully.
|
||
|
||
|
||
This method extends the V30H address capability by 4 bits to produce two 24 bit address bus ranges, one
|
||
for RAM and one for ROM. This gives an affected linear address range of 32 MBytes. The 16 MByte
|
||
RAM space is decoded into 4 Chip selects allowing up to 8 x 16 Mbit RAM devices (2 per chip select as
|
||
16 bit wide). The 16 MByte ROM space is decoded into two chip selects each selecting 8 MBytes each,
|
||
one for mask ROM and one for FLASH memory.
|
||
|
||
|
||
The physical address map for the V30H now looks like this:-
|
||
|
||
|
||
00000 - SFFFF | Maps to physical bottom 384K of the 16 Mbyte RAM space.
|
||
60000 - 6FFFF | Maps to 64K RAM segment selected by page register PSELO.
|
||
70000 - 7FFFF | Maps to 64K RAM segment selected by page register PSEL1.
|
||
80000 - 8FFFF | Maps to 64K ROM segment selected by page register PSEL2.
|
||
90000 - 9FFFF | Maps to 64K ROM segment selected by page register PSEL3.
|
||
A0000 - FFFFF | Maps to physical top 384K of the 16 Mbyte ROM space.
|
||
|
||
|
||
= Se
|
||
|
||
|
||
Although the V30H microprocessor is rated at clock speeds of up to 16 MHz, the Series 3 machine is
|
||
currently limited to a clock speed of 3.84 MHz. This is due to the fact that ASICi accesses the ROM as
|
||
two 8 bit bytes to assemble a 16 bit word for the V30H. This equates to a required ROM access speed of
|
||
|
||
|
||
approximately 250 nSec for a 3.84 MHz clock. Readily available mask ROM's have an access speed of
|
||
200 nSec which currently limits the clock speed of Series 3.
|
||
|
||
|
||
ASIC9 supports 16 bit wide accesses to memory space which allows a doubling of the clock speed for the
|
||
same ROM access time. In addition ASIC9 will support programmable wait states so that faster clock
|
||
speeds can be used with slow ROM's or RAM's.
|
||
|
||
|
||
more closely to the bus controller. This is now possible as they are both in the same chip. The serial
|
||
controller can now automatically hold the processor (by stopping the CPU clock) if it attempts to issue a
|
||
command to the controller whilst it is busy. This reduces to zero the overhead involved in determining
|
||
this condition. This technique should also enhance the speed that Flash memory devices can be written
|
||
to.
|
||
|
||
|
||
Addition of hardware 32 b =—séC
|
||
The ASICI/ASIC2 implementation of the SIBO architecture uses the FRC (Free running counter) to
|
||
maintain time while the CPU is powered down (in standby). This means the CPU must wake up at a
|
||
periodic rate (approx 8 hours) to keep time, if the CPU cannot start (no main batteries) time is lost. To
|
||
overcome this limitation AS/C9 contains a separate 32 bit real time clock that will continually maintain
|
||
the system time independently from the CPU. This counter will be clocked at 1 Hz so its maximum range
|
||
will be 232 seconds or approx 136 years.
|
||
|
||
|
||
1 THE PRINCIPAL CHIP SET
|
||
EEE
|
||
|
||
|
||
ASIC9 contains a 16 FIFO buffer to reduce the CPU overhead involved in playing or recording sounds
|
||
via the CODEC device.
|
||
|
||
|
||
ASIC9 contains the logic to bring the system out of the standby state if any of a set number of row inputs
|
||
goes high. This allows Switch on via the membrane key pads.
|
||
|
||
|
||
The 16 MByte paged ROM address will be split into twe sections each 8 MBytes in size. It is intended
|
||
that one section is for mask ROM one for FLASH memory.
|
||
|
||
|
||
ASIC9 contains an additional FRC (Free Running Counter). This FRC is functionally identical to the
|
||
current FRC but is indented for general user use and is not used by EPOC.
|
||
|
||
|
||
This second FRC can be clocked from either 512 KHz or 1024 Hz. This extends the use of the FRC by
|
||
providing a counter with a resolution of 1 mSec and a range of just over one minute. This could help
|
||
software time events in the mSec range i.e. a stopwatch.
|
||
|
||
|
||
The mapping of the two video maps has been improved to reduce the overhead that grey scales impose on
|
||
software. This improved scheme supports only one grey level together with black and white. The second
|
||
video map is an attribute map and would have the effect of dimming only those pixels that are set i.e.
|
||
black.
|
||
|
||
|
||
“
|
||
|
||
|
||
ASIC9 contains three serial control registers and three read data registers. This allows independent
|
||
expansion devices to be added to either SSD slot.
|
||
|
||
|
||
The main advantage of triple registers is that a multiple-mode pack read can be interrupted at anytime by
|
||
a read or write to any of the other serial channels without loss of setup and data, for example servicing an
|
||
RS232 interrupt from either SSD slot.
|
||
|
||
|
||
The ASICI/ASIC2 implementation of the SIBO architecture positions the two video maps so that they are
|
||
separated by a fixed address space (16K 4000H). This restriction is overcome in ASIC9 by Starting the
|
||
second video map directly after the first video map regardless of the size of the video maps.
|
||
|
||
|
||
in SS
|
||
|
||
|
||
Two active low external interrupt inputs are provided by ASJC9 which can be connected to the VBACK
|
||
outputs on two SSD sockets. This will allow SSD sized expansion devices to be fitted internally to the
|
||
Series 3a.
|
||
|
||
|
||
The Interrupt allocation has been changed in AS/C9 so that sound processing is serviced at the highest
|
||
priority. Interrupts are allocated as follows:-
|
||
|
||
|
||
CSINT CODEC sound interrupt.
|
||
TINT 32 Hz tick interrupt.
|
||
SSINT Serial slave interrupt.
|
||
EINTO External interrupt input 0.
|
||
|
||
|
||
EINT1 External interrupt input 1 (inverted).
|
||
EINT2 External interrupt input 2 (inverted).
|
||
FRC1OI FRC1 overflow interrupt .
|
||
FRC20I1 FRC2 overflow interrupt.
|
||
|
||
|
||
PSU subsystem
|
||
|
||
|
||
SIBO architecture power supplies all differ depending on the system requirements. MC and HC power
|
||
supplies have higher current ratings to support a wide variety of expansion devices and are based around
|
||
7.2 volt NiCd batteries. The Series 3 and its derivatives have a lower current rating and are based around
|
||
two 1.5 volt alkaline batteries.
|
||
|
||
|
||
MC and HC power supplies are based on a full custom liner ASIC known as ASIC3. This custom chip is
|
||
manufactured by Maxim and has the Maxim part number MAX616. The power supply provides a
|
||
number of switched power rails from one unregulated supply rail known as Vsup. This supply is
|
||
typically connected to the main battery in the system and can be in the range 5.5 to 12 volts. These
|
||
supply rails are derived from Vsup from either PNP pass transistor linear regulators or from switch mode
|
||
regulators. Series 3 power supplies generate a sub-set of the rails listed below from a number of switch
|
||
mode regulators.
|
||
|
||
|
||
SIBO architecture power supplies all operate in four principal states, these are; standby, backup idle and
|
||
operating.
|
||
|
||
|
||
Th : 2
|
||
|
||
|
||
In the standby state the main oscillator and the processor are shut down. ASICI, ASIC2 and the memory
|
||
are powered and the real time oscillator is running to keep time. The timer in ASJCI is used in this mode
|
||
to keep time while the processor is powered down. All other supply rails are switched of in this state.
|
||
|
||
|
||
The backup state only exists when the main battery supply has failed or is not present. State is the
|
||
same as the standby state except that Vccl is now powered from the backup battery input and switching
|
||
to the operating state is inhibited.
|
||
|
||
|
||
In the idle state the processor is powered up and the main system oscillator is running: the switchable
|
||
supply rails may be on depending on software instructions. The processor clock is stopped and the
|
||
processor is idle and waiting for an event i.e. an interrupt. This means that the bus is not active apart
|
||
from LCD screen refresh accesses.
|
||
|
||
|
||
ating state __—sdiziéts =—i—<iéis—sSCséséséS<Sié<S;S
|
||
The operating state is the same as the idle state except that the processor clock is running and the bus is
|
||
active.
|
||
|
||
|
||
ee l—“OCONONONONRO#NONONNONCONOCNCCCi«SC.CisikiséstsC«sisisCCisés..SN
|
||
Vccl is a nominal +5 volt supply that is not programmable and is present in all states. On MC and HC
|
||
power supplies it is derived from Vsup via a PNP pass transistor, the base drive of which is supplied by
|
||
|
||
|
||
—e
|
||
|
||
|
||
1 THE PRINCIPAL CHIP SET
|
||
— ee EEEESSSSSSSSSSSSSSSSsshsFsese
|
||
|
||
|
||
ASIC3, this configuration is the same for all the linear regulators. On Series 3 power supplies it is
|
||
derived from a DC to DC converter and on ASIC9 based systems the nominal voltage is 3.3 volts.
|
||
|
||
|
||
Vccl supplies ASIC] and ASIC2 or ASIC9 plus all the memory. The Vccl supply is current limited to a
|
||
few hundred micro-amps when the system is in the standby state.
|
||
|
||
|
||
Vcc2 is a +5 volt supply that is either derived from Vsup in the same way as Vccl or from a DC to DC
|
||
converter. Vcc2 is disabled when the system is in the standby state and is automatically switched on when
|
||
the operating or idle state is entered. Vcc2 powers the processor and any other devices that can be shut
|
||
down in the standby state. Vcc2 is also connected to the expansion ports for powering peripheral devices.
|
||
Vecc2 is fixed at 5 volts even in a 3.3 volt system.
|
||
|
||
|
||
Vcc3 is a software switchable supply. It is either 5 volts or 3.3 volts depending on the voltage of Vccl. It
|
||
is connected to the LCD display module and powers the display drivers.
|
||
|
||
|
||
Vccé4 is a software switchable +5 volt supply. It is connected to the positive supply to the sound sub-
|
||
system. It is only present in MC and HC power supplies.
|
||
|
||
|
||
VecS is a software switchable +5 volt supply that is either derived from Vsup in the same way as Vccl
|
||
or switched from Vcc2. It is connected to the 5 volt supply pin on the external SSD slots.
|
||
|
||
|
||
Veel is a software switchable negative supply rail which is connected to the LCD module to provide the
|
||
|
||
|
||
LCD bias voltage. The voltage of Veel can by programmed in software to provide software adjustment
|
||
of the LCD contrast. Veel is generated using a fly-back switch mode regulator. The voltage generated is
|
||
determined by comparing the feedback voltage to the output of a DAC.
|
||
|
||
|
||
able negative supply rail which is connected to the negative supply of the sound
|
||
|
||
|
||
Vee2 is a software switch:
|
||
|
||
|
||
sub-system. Vee2 is specified as -5 volts plus or minus 5% and is generated from Vsup using a fly-back
|
||
switch mode regulator which is controlled by ASIC3. Vee2 is only present on MC and HC power
|
||
supplies.
|
||
|
||
|
||
Vh is a software switchable positive supply rail which is connected to the SSD slots. It is used in the
|
||
SSD's to provide the programming voltage needed to write and format Flash memory devices. Vh is
|
||
generated using a fly-back switch mode regulator is specified to be +16 volts.
|
||
|
||
|
||
CHAPTER 2
|
||
|
||
|
||
THE SIBO SERIAL PROTOCOL
|
||
|
||
|
||
The SIBO serial protocol is a general purpose method of bidirectional serial data transfer. It has been
|
||
designed to communicate between a controlling device and a number of slave devices
|
||
|
||
|
||
The interface consists of 2 wires as follows:
|
||
CLK Clock output from the controller to the slaves. Nominally 3.84 MHz.
|
||
DATA A bidirectional synchronous data line.
|
||
|
||
|
||
The data is transferred using a series of 12 bit frames including 8 data bits each. This equates to a
|
||
theoretical maximum data transfer rate of approximately 312 Kbytes/second. Other bits of the frame
|
||
contain control information.
|
||
|
||
|
||
The "system" is generically defined by 2 protocol layers:
|
||
|
||
The Physical layer defining the hardware interface and frame structure.
|
||
|
||
The Transport layer defines system control and register transfers between the controller and the slaves.
|
||
These layers are described in detail in the next two sections.
|
||
|
||
|
||
Using this system a large number of higher level implementations can be defined. Initially these will
|
||
include:
|
||
|
||
|
||
1) An eight channel controller. This will be embodied within all SIBO computers to allow up
|
||
to 8 isolated channels to be accessed.
|
||
|
||
|
||
2) Power control IC. This is also internal to the computers and operates as a slave.
|
||
3) Memory pack. This is an external plug-in device operating as a slave.
|
||
|
||
|
||
In normal use the controller will communicate to slaves in a point to point configuration. Multidrop
|
||
configurations with a number of slaves attached to one channel of the controller are also supported.
|
||
|
||
|
||
ES ee ee ee ee ee
|
||
Hardware Interface
|
||
|
||
This section specifies the timing and hardware required by the SIBO serial protocol.
|
||
|
||
This consists of two lines that switch at SV CMOS voltage levels:-
|
||
|
||
CLK = Aclock output from the controller to the slaves. Nominally 3.84 MHz.
|
||
|
||
DATA A bidirectional synchronous data line.
|
||
|
||
|
||
This line is used to synchronously clock data between the controller and slaves. It is always output from
|
||
the controller.
|
||
|
||
|
||
The clock should only be active during the transfer of data. At all other times it is tristate pulled low.
|
||
|
||
|
||
11
|
||
|
||
|
||
HARDWARE REFERENCE
|
||
|
||
|
||
Clock Timing Parameters
|
||
Symbol
|
||
Tckh
|
||
Tckl Width of Clock Low
|
||
|
||
|
||
Teyc Cycle time of clock
|
||
Fck Clock Frequency
|
||
|
||
|
||
Width of Clock High
|
||
|
||
|
||
This is a bidirectional line used to transfer data synchronously between the controller and slaves. The
|
||
direction of the data line is not determined by the physical layer but by the control information in the
|
||
transport layer. This is described in the next section.
|
||
|
||
|
||
When no data transfers are in progress the data line is always set to input on both the controller and
|
||
slaves. This line is pulled low.
|
||
|
||
|
||
Data Timing Parameters
|
||
|
||
|
||
Data Received by Controller
|
||
|
||
|
||
Trdset Data set-up time
|
||
Trdhold Data hold time
|
||
|
||
|
||
Trdset Data set-up time
|
||
Trdhold Data hold time
|
||
|
||
|
||
Data is changed on the falling edge of clock by the transmit device and latched into the receiving device
|
||
on the rising edge of clock.
|
||
|
||
|
||
The Physical layer
|
||
This section specifies the low level protocol of the SIBO serial protocol.
|
||
|
||
|
||
The physical layer protocol consists of a series of 12 bit frames. There are four types of frames:
|
||
|
||
|
||
Null frames Transmitted by controller to synchronize slaves.
|
||
Control frames Control information transmitted by controller to slaves.
|
||
Data output frames Data frame transmitted by controller to slaves.
|
||
|
||
Data input frames Data frame received by controller from a slave.
|
||
|
||
|
||
Name ST CTL Ii DO D3 D4 D5 D6 D7
|
||
|
||
|
||
2 THE SIBO SERIAL PROTOCOL
|
||
|
||
|
||
ST Start bit. This bit goes high to indicate the start of a valid frame.
|
||
|
||
CTL Control bit. When low indicates this is a control frame. High indicates a data frame.
|
||
It Idle bit. Used to turn around direction of data line. Normally Low.
|
||
|
||
DO-D7 Data bits. Used to turn around direction of data line. Normally low.
|
||
|
||
I2 Idle bit.
|
||
|
||
|
||
This is a special frame transmitted by the controller to ensure all slaves are synchronized. It is generated
|
||
by transmitting 12 clock pulses with the data line set to input. Since the data line is pulled low this
|
||
results in 12 zeros being transmitted.
|
||
|
||
|
||
Control frame. _
|
||
|
||
|
||
This frame is transmitted from the controller to one or more slaves. The data line is an output from the
|
||
controller throughout the whole frame.
|
||
|
||
|
||
The bits in the frame have the following value in a control frame.
|
||
|
||
|
||
ST Start bit. This bit goes high to indicate the start of a valid frame.
|
||
CTL Control bit. Low to indicate this is a control frame.
|
||
|
||
I] Idle bit. Set low.
|
||
|
||
D0-D7 Data bits. 8 bits of control information.
|
||
|
||
12 Idle bit. Set low.
|
||
|
||
|
||
The bits in the frame have the following value in a data output frame.
|
||
|
||
|
||
ST Start bit. This bit goes high to indicate the start of a valid frame.
|
||
CTL Control bit. High to indicate this is a data frame.
|
||
|
||
I1 Idle bit. Set low.
|
||
|
||
DO0-D7 Data bits. 8 bits of transmitted data.
|
||
|
||
I2 Idle bit. Set low.
|
||
|
||
|
||
This frame is received by the controller from a slave. The data line is an output from the controller for
|
||
cycles 1 and 2 and input to the controller for cycles 4 to 11.
|
||
|
||
|
||
The bits in the frame have the following value in a data input frame.
|
||
|
||
|
||
ST Start bit. Output from controller. This bit goes high to indicate the start of a valid
|
||
frame.
|
||
|
||
CTL Control bit. Output from controller. High to indicate this is a data frame.
|
||
|
||
Il Idle bit. Used to turn around direction of data line. Both controller and slave should
|
||
|
||
|
||
tristate the data line during this bit. This bit should be low due to pull down
|
||
resistor on data line. The controller changes the data line from output to input
|
||
at the end of cycle 2. The slave changes the data line from input to output at
|
||
the start of cycle 4.
|
||
|
||
|
||
Data bits. Output from slave 8 bits of data transmitted by slave. Controller sets data line
|
||
to input during these bits.
|
||
|
||
|
||
13
|
||
|
||
|
||
HARDWARE REFERENCE
|
||
|
||
|
||
I2 Idle bit. Used to turn around direction of data line. Both controller and slave should
|
||
tristate the data line during this bit. Should be low due to pull down resistor on
|
||
data line. The slave changes data line from output to input at the end of cycle
|
||
11.
|
||
|
||
|
||
SLAVE
|
||
|
||
|
||
Condition
|
||
|
||
|
||
Outside Frame
|
||
Null frame
|
||
Control Frame
|
||
Data output from controller
|
||
Data input to controller:-
|
||
Cycles 1-2
|
||
Cycle 3
|
||
Cycles 4-1
|
||
Cycle 12
|
||
|
||
|
||
Key T Tristate
|
||
I Input
|
||
oO Output
|
||
|
||
|
||
SSS eee ee ee ee ae eer
|
||
The Transport layer
|
||
|
||
|
||
This section specifies the transport level protocol that operates above the SIBO serial communication
|
||
physical layer.
|
||
|
||
|
||
The transport layer protocol controls the serial communication between the SIBO Protocol Controller
|
||
(SPC) and a number of SIBO Protocol Slave (SPS) devices. The following rules apply:
|
||
|
||
|
||
1) The interface is controlled by the writing of control bytes from the controller to the slaves.
|
||
Control bytes cannot be written by the slaves. Unsolicited data cannot be sent from the slave
|
||
to the controller.
|
||
|
||
|
||
2) The controlling device contains two registers to communicate to the slaves. These are the
|
||
control register (byte, write only) and the Data register (byte or word, read/write).
|
||
|
||
|
||
Control bytes are transmitted to the slaves by writing to the control register.
|
||
|
||
|
||
The format of the control byte is as follows:-
|
||
|
||
|
||
The control word can have 2 distinct formats depending on the setting of bit 7 the Select (S) bit:
|
||
|
||
|
||
Select = 0 This is the slave select mode. This mode is for selecting, deselecting and
|
||
resetting slaves.
|
||
|
||
|
||
Select = 1 This is the slave control mode. This mode is for communicating with a slave
|
||
which has been previously selected using the select slave command.
|
||
|
||
|
||
14
|
||
|
||
|
||
2 THE SIBO SERIAL PROTOCOL
|
||
|
||
|
||
Key: R = single reset bit, IIIIII = 6 bit ID field.
|
||
|
||
|
||
The 6 bit ID field is a property only of the slave. No slave may have an ID of zero, hence there can be 63
|
||
different slaves connected to one controller.
|
||
|
||
|
||
The reset bit (R) controls whether the slave(s) are selected or reset. If R = 0 slave(s) are reset, R = 1
|
||
slave(s) are selected.
|
||
|
||
|
||
Slave select control bytes can be summarised by the following table:
|
||
|
||
|
||
0 0 0 Reset all slaves
|
||
|
||
0 0 xx< >0 Reset specific slave with ID = xx
|
||
|
||
0 1 0 Deselect slave (does not reset slave)
|
||
|
||
0 1 xx< >0 Select slave with ID=xx and read slave info (see below).
|
||
|
||
|
||
The Reset function is dependant on the slave. It would normally put the slave into a known passive reset
|
||
State.
|
||
|
||
|
||
Select Slave with ID=xx (S=0,R=1)
|
||
|
||
This is a special command that causes a slave with ID=xx to transmit to the controller an 8 bit
|
||
information field. This field depends entirely on the slave but must be non zero. A reply of 0 indicates
|
||
that there is no slave of the requested ID present.
|
||
|
||
|
||
command described above.
|
||
|
||
|
||
The format of the control word in slave select mode is as follows:
|
||
|
||
|
||
Key
|
||
|
||
R/W Read/write select. 0 = write, 1 = read
|
||
|
||
B/W Data transfer size. 0 = 1 byte transfer, 1 = word (2 byte transfer).
|
||
S/M Single/Multi transfer mode. 0 = single, 1 = multibyte.
|
||
|
||
XXXX 4 bits of data to slave.
|
||
|
||
|
||
Note the meaning of the 4 bits of data (XXXX) is entirely dependent on the slave.
|
||
|
||
|
||
The settings of R/W,B/W,S/M bits in the control word determine the size, type and direction of
|
||
subsequent data transfers in the following manner:
|
||
|
||
|
||
15
|
||
|
||
|
||
HARDWARE REFERENCE
|
||
—_— gs eeeSSSEeeeSSSSSSSSFSSSSSMSSN
|
||
|
||
|
||
2
|
||
2
|
||
|
||
|
||
S/M
|
||
write a single byte to slave
|
||
write a number of single bytes to slave
|
||
write a byte pair to slave
|
||
|
||
|
||
write a number of byte pairs to slave
|
||
|
||
|
||
read a number of single bytes from slave
|
||
|
||
|
||
read a byte pair from slave
|
||
|
||
|
||
= SY —& -&§ CO FO OC OO
|
||
|
||
|
||
0
|
||
1
|
||
0
|
||
1
|
||
0 read a single byte from slave
|
||
1
|
||
0
|
||
1
|
||
|
||
|
||
- Fe OF 0O KF &§ CO 0
|
||
|
||
|
||
read a number of byte pairs from slave
|
||
Write a single byte
|
||
|
||
|
||
This command readies the currently selected slave to receive a byte of data and sets up the controller so
|
||
that the next byte (or the LSB of a word) written to its data register will be transmitted to that slave.
|
||
Anything further written to the controller's data register will have no effect.
|
||
|
||
|
||
Write a number of single bytes
|
||
|
||
|
||
This command readies the currently selected slave to receive a number of sequential bytes of data. The
|
||
slave will expect to receive data bytes until another control byte is received. The controller is set up so
|
||
that the next byte (or the LSB of a word) written to its data register will be transmitted to that slave. All
|
||
subsequent bytes written to the controller's data register will be transmitted to the slave. This will
|
||
continue until another byte is written to the controller's control register.
|
||
|
||
|
||
Write a byte pair
|
||
|
||
|
||
This command readies the currently selected slave to receive two bytes of data and sets up the controller
|
||
so that the next word written to its data register will be transmitted to that slave (LSB first). Anything
|
||
further written to the controller's data register will have no effect.
|
||
|
||
|
||
Write a number of byte pairs
|
||
|
||
|
||
This command readies the currently selected slave to receive a number of sequential byte pairs of data.
|
||
The slave will expect to receive byte pairs until another control byte is received. The controller is set up
|
||
so that the next word written to its data register will be transmitted to that slave (LSB first). All
|
||
subsequent words written to the controller's data register will be transmitted to the slave. This will
|
||
continue until another byte is written to the controller's control register.
|
||
|
||
|
||
Read a single byte
|
||
|
||
|
||
This command triggers a byte to be transmitted from the selected slave to the controller. This byte can
|
||
then be read from the LSB of the controller's data register. Further reads of the controller's data register
|
||
will return the same data but have no effect on the protocol.
|
||
|
||
|
||
Read a number of single bytes
|
||
|
||
|
||
This command triggers a byte to be transmitted from the selected slave to the controller. This byte can
|
||
then be read from the LSB of the data register. This read will trigger the next byte to be transmitted to
|
||
the data register of the controller. All subsequent reads of the controller's data register will trigger
|
||
further bytes to be transmitted to the controller. This will continue until another byte is written to the
|
||
controller's control register.
|
||
|
||
|
||
Read a byte pair
|
||
|
||
|
||
This command triggers a byte pair to be transmitted from the selected slave to the controller. This word
|
||
can then be read from the controller's data register. Further reads of the controller's data register will
|
||
return the same data but have no effect on the protocol.
|
||
|
||
|
||
Read a number of byte pairs
|
||
|
||
|
||
This command triggers a byte pair to be transmitted from the selected slave to the controller. This word
|
||
can then be read from the controller's data register. This read will trigger the next byte pair to be
|
||
transmitted to the data register of the controller. All subsequent reads of the controller's data register will
|
||
trigger further byte pairs to be transmitted to the controller. This will continue until another byte is
|
||
written to the controller's control register.
|
||
|
||
|
||
16
|
||
|
||
|
||
2 THE SIBO SERIAL PROTOCOL
|
||
|
||
|
||
wn below. The time is given in SIBO
|
||
pack protocol clock cycles. The length of a clock cycle is nominally 260 nanoseconds for a clock
|
||
frequency of 3.84 MHz.
|
||
|
||
|
||
Receive and process the control byte 12 cycles
|
||
Byte transfer to or from slave 12 cycles
|
||
Byte pair transfer to or from slave 24 cycles
|
||
|
||
|
||
When writing to the controller's data and control registers the following rules apply:-
|
||
|
||
|
||
1) After writing to the control register there must be a delay of at least 12 cycles before the
|
||
data register is accessed or another control word is written.
|
||
|
||
|
||
2) To read a word from the data register after the command to read byte pair is issued there
|
||
must a delay of at least 12 (for control byte) + 24 (for the byte pair transfer) = 36 cycles.
|
||
|
||
|
||
3) To perform a multiple byte pair write there must be a delay of at least 12 cycles after the
|
||
command is written to the control register before the first word can be written to the data
|
||
register and a delay of at least 24 cycles between subsequent writes to the data register.
|
||
|
||
|
||
A slave can be in one of 5 states. Note a control byte can be received and interpreted at any time.
|
||
1) Waiting to receive a data byte or control byte
|
||
2) Waiting to receive a data byte pair or control byte
|
||
3) Waiting to transmit a data byte or control byte
|
||
4) Waiting to transmit a data byte pair or control byte
|
||
|
||
|
||
5) Waiting to receive control byte only
|
||
|
||
|
||
The following table shows the state after each control word is received
|
||
|
||
|
||
S R Dow Slave select
|
||
0 0 0 Reset all
|
||
|
||
0 0 <>0 Reset slave
|
||
| 0 Deselect slave
|
||
Oo 1 <>0 Select slave
|
||
|
||
S RW B2B SM XXXx
|
||
|
||
1 0 0 0 x write byte
|
||
|
||
1 OQ 0 1 x write bytes
|
||
|
||
1 0 1 0 x write byte pair
|
||
1 0O 1 1 x write byte pairs
|
||
1 1 0 0 x read byte
|
||
|
||
1 1 0 1 x read bytes
|
||
|
||
1 1 1 0 x read byte pair
|
||
|
||
1 1 1 1 x read byte pairs
|
||
|
||
|
||
17
|
||
|
||
|
||
CHAPTER 3
|
||
|
||
|
||
THE SIBO EXPANSION PorTS
|
||
|
||
|
||
The SIBO architecture allows for two types of expansion device, extended internal expansion and reduced
|
||
external expansion. Extended internal expansion slots provide direct I/O with the processor, a SIBO
|
||
serial channel, and connection to the power supply. It allows for higher powered expansion devices to be
|
||
added by including a direct connection to the main 7.2 volt battery. The MC and HC products both
|
||
support two independent extended internal expansion slots. Reduced external expansion is based on a
|
||
single SIBO serial channel only and has very limited power available ( < 25 mA ). The Series 3 and 3a
|
||
supports a single reduced external expansion slot only.
|
||
|
||
|
||
———E SSS eee ee ee eee
|
||
Extended internal expansion
|
||
|
||
|
||
98148-1182
|
||
EXPANSION DEVICE
|
||
|
||
|
||
COMPONENT SIDE
|
||
|
||
|
||
99148-1123
|
||
|
||
|
||
SIBO COMPUTER
|
||
|
||
|
||
Figure 2
|
||
|
||
|
||
The 26th position is a polarising key and should be left blank. The correct mating connector on the
|
||
expansion device is made up from a number of Molex C-Grid series 90148 connectors. Pins 1 and 2 are
|
||
|
||
|
||
19
|
||
|
||
|
||
HARDWARE REFERENCE
|
||
|
||
|
||
GND and should have there own connector placed nearer the board edge to ensure the GND connection
|
||
is made first when the expansion device is inserted. The required connectors are Molex 90148-1102 for
|
||
the GND contacts and Molex 90148-1123 for the signal contacts.
|
||
|
||
|
||
Should mate first when device inserted
|
||
|
||
Should mate first when device inserted
|
||
B CMOS] 8 bit multiplexed address and data bus pulled low with 100 K resistors
|
||
B CMOS
|
||
|
||
|
||
O CMOS} I/O write strobe - active high, data valid on falling edge of IOWR
|
||
O CMOS] I/O read strobe - high when device can place valid data on ADO-AD7
|
||
O CMOS| External Expansion Select - high during I/O cycles to expansion device
|
||
Reserved
|
||
Reserved
|
||
Reserved
|
||
Used to enable reprograming of internal system Flash memory
|
||
Unregulated battery voltage - present all the time
|
||
I CMOS | Active high interrupt input
|
||
I CMOS | Active low input pulled up to Vcci - pull low to switch machine on
|
||
B CMOS| SIBO serial protocol data line - pulled low
|
||
T CMOS| SIBO serial protocol clock line - Hi-Z in standby needs a pull down
|
||
Power
|
||
Power | +5 volt supply, switched off in standby. Max current available = 50 mA
|
||
|
||
|
||
The signal types are:
|
||
|
||
O CMOS CMOS output to the expansion device.
|
||
|
||
B CMOS CMOS bi-directional line to the expansion device.
|
||
T CMOS CMOS tri-state output to the expansion device.
|
||
|
||
1 CMOS CMOS input from the expansion device.
|
||
|
||
|
||
All the CMOS signals including the ADO-AD7 bus are buffered from the main system busses and so
|
||
present a load of one HC series logic gate.
|
||
|
||
|
||
Expansion devices can be connected to direct processor I/O space using the following signals; ADO-AD7,
|
||
ALE, IOWR, IORD, EES and INTR.
|
||
|
||
|
||
ADO-AD7 is the least significant half of the multiplexed address and data bus, this means that up to 128
|
||
I/O addresses are available for each expansion device. As only the least significant half of the bus is
|
||
available and no bus conversion is done only even addresses can be used.
|
||
|
||
|
||
ALE must be used to latch the address from ADO-AD7 for devices that require a stable address. The
|
||
address is valid on the falling edge of ALE. Note that AO will always be low for valid writes to the
|
||
expansion device and as such should not be used as an address line, Al should be used as the lowest
|
||
order address line. AO can be used as an additional enable signal to stop odd I/O accesses disturbing the
|
||
expansion device (see example 1).
|
||
|
||
|
||
EES is the External Expansion Select and is high during all I/O accesses to the expansion device, i.e. for
|
||
I/O reads and writes to address range 100 to 1FF hex. for expansion port 1, and 200 to 2FF for
|
||
expansion port 2.
|
||
|
||
|
||
20
|
||
|
||
|
||
3 THE SIBO EXPANSION PORTS
|
||
|
||
|
||
IOWR is an active high signal which is high during all I/O write bus cycles. The data on ADO-AD7 is
|
||
guaranteed to be stable before the rising edge of IOWR and after the falling edge of IOWR.
|
||
|
||
|
||
IORD is an active high signal which is high during all I/O read bus cycles. The ADO-AD7 bus is
|
||
guaranteed to be tri-state before the rising edge of IORD and after the falling edge of IORD. The
|
||
expansion device must present valid data on the bus when IORD is high, see the timing details below.
|
||
|
||
|
||
INTR is an active high interrupt input to ASJC1. This can be used as a directly readable bit or as a
|
||
dedicated interrupt input. It must not be driven high when the system is in the standby state as this input
|
||
is pulled down and will cause excessive standby current consumption.
|
||
|
||
|
||
Figure 3 shows the timing of the I/O write and read cycles.
|
||
|
||
|
||
1/0 WRITE CYCLE :
|
||
: /VVV ,
|
||
ADB-AD7 VALID _ADDRX X XXX VALID WRITE DATA :
|
||
|
||
|
||
ALE
|
||
|
||
|
||
Fes
|
||
|
||
|
||
ALE
|
||
|
||
|
||
EES
|
||
|
||
|
||
IORD
|
||
|
||
|
||
Address set up time
|
||
|
||
Address hold time
|
||
|
||
Write data set up time
|
||
|
||
Write cycle pulse width
|
||
|
||
Write data hold time
|
||
|
||
Time from Hi-Z to data active
|
||
Read cycle pulse width
|
||
|
||
Read data set up time
|
||
|
||
Read data hold time
|
||
|
||
|
||
Note the typical values given are for an MC with a system oscillator of 15.36 MHz, the HC times will be
|
||
approximately twice as long. The minimum times given are for projected higher speed MC devices with
|
||
oscillator frequencies of up to 23.04 MHz.
|
||
|
||
|
||
21
|
||
|
||
|
||
HARDWARE REFERENCE
|
||
a kw eS
|
||
|
||
|
||
1.536 MHz regardless of the system clock frequency. This frequency is a multiple of the SLD clock rate
|
||
and of all normal RS232 baud rates.
|
||
|
||
|
||
Two power supplies are available for expansion devices these are Vcc2 and Vsup.
|
||
|
||
|
||
Vec2 is a +5 volt supply that is derived from Vsup. Vec2 is switched off when the system is in the
|
||
standby state and is switched on when the operating or idle state is entered. Each expansion device can
|
||
draw up to 50 mA from Vcc2.
|
||
|
||
|
||
If an expansion device requires more than 50 mA or cannot be powered down when the system is in the
|
||
standby state the Vsup power supply must be used. Vsup is the unregulated supply directly from the main
|
||
system batteries or from the DC jack input. It will be in the range 5.5 to 12 volts under normal
|
||
conditions. To use Vsup the expansion device must regulate Vsup to 5 volts with a low drop-out linear
|
||
regulator. Care must be taken to not be active and driving any signals high when the system is in the
|
||
standby state as Vsup is always present. This can be achieved either in software or by using Vcc2 as a
|
||
signal indicating the active state.
|
||
|
||
|
||
SSE, EE ee ae ee eee
|
||
|
||
|
||
Reduced external expansion
|
||
|
||
|
||
The reduced expansion port is made up of a 6 way two row connector spaced on a 2 x 3 way 0.1 inch
|
||
pitch. Figure 4 shows the physical connector numbering.
|
||
|
||
|
||
Looking into Series 3 / 3a
|
||
|
||
|
||
Figure 4
|
||
|
||
|
||
MSD Master SIBO serial protocol data line - pulled low
|
||
MCLK Master SIBO serial protocol clock line - low in standby
|
||
Vec +5 volt supply, switched off in standby. Limited to 25 mA
|
||
GND Signal ground, this signal should mate first when connector inserted
|
||
SSD/INT Slave SIBO serial data line or active high interrupt input
|
||
Slave SIBO serial clock line or active high switch on input
|
||
|
||
|
||
MSD and MCLK form a single master SIBO serial protocol channel, this is normally channel 7. The
|
||
serial channel clock can be continuously enabled to provide a free running clock for expansion devices.
|
||
The frequency is fixed at 1.536 MHz regardless of the system clock frequency. SDS/INT and
|
||
SCK/EXON are both dual function pins. SDS and SCK form a single slave SIBO serial protocol channel,
|
||
this can be combined with MSD and MCLK to form a bidirectional high speed data link. SDS/INT can
|
||
also be used as an active high interrupt input. The function of SDS/INT can be programmed in ASIC2 or
|
||
ASIC9. A rising edge on the SCK/EXON input will bring the system out of the Standby state into the
|
||
operating state. VCC is a +5 volt supply that is switched off when the system is in the standby state and
|
||
|
||
|
||
22
|
||
|
||
|
||
3 THE SIBO EXPANSION PORTS
|
||
|
||
|
||
is switched on when the system is in the operating or idle state. The maximum current that can be drawn
|
||
is 25 mA.
|
||
|
||
|
||
ha Se ee ee eS ee a el
|
||
Example expansion devices
|
||
|
||
|
||
Two examples are given to illustrate using the direct I/O expansion signals present in an extended SIBO
|
||
expansion port. A further example is given using a SIBO serial channel for both reduced and extended
|
||
expansion slots.
|
||
|
||
|
||
ExaER one is a ‘ile 8 bit read/write port. 8 LEDs can be set ie an OUT instruction and the state of
|
||
an 8 bit DIL switch can be read by an IN instruction. Figure 5 shows the schematic of such a port.
|
||
|
||
|
||
=
|
||
Eee te a tae a [ia]
|
||
=I a [ae
|
||
vs iis
|
||
4 274 2ag Le) 2
|
||
16p
|
||
Bch ai ji
|
||
26) IT
|
||
8x100K
|
||
|
||
|
||
GND GNO GND GND GND GND GND GNO
|
||
|
||
|
||
8 x Lav
|
||
current LEOs
|
||
|
||
|
||
cs
|
||
LOOnF
|
||
|
||
|
||
Figure 5
|
||
|
||
|
||
Note that the port is powered from Vcc2 which has a maximum current budget of 50 mA so low current
|
||
LEDs must be used.
|
||
|
||
|
||
IC3B latches the state of ADO to provide a stable AO line, this is used as an additional enable signal, so
|
||
that only even I/O cycles will effect the state of the port. IC2A combines AO, EES and IORD to provide
|
||
a negative going pulse during any even read to the expansion port address range. IC2B combines AO,
|
||
EES and IOWR to provide a negative going pulse during any even writes to the expansion port address
|
||
range. IC2C just inverts the sense of ALE so that address can be latched on the rising edge by IC3B.
|
||
|
||
|
||
wo - 16 channel ADC |
|
||
|
||
Example two is a 16 channel analog input interface. It is based on the National Semiconductor part
|
||
ADC0816. The interface is arranged so that a write to the expansion port address range will start a
|
||
conversion and select the required analog channel to read. The interrupt input (INTR) is connected to the
|
||
EOC signal to generate an interrupt when the conversion is complete.
|
||
|
||
|
||
Figure '6 ‘shows the schematic of the 16 channel analog interface.
|
||
|
||
|
||
23
|
||
|
||
|
||
HARDWARE REFERENCE
|
||
|
||
|
||
MC/HC EXPANSION PORT
|
||
|
||
|
||
i cL c2 i c3 ca cs
|
||
— 6V3 100nF L100nF 406nF 100nF
|
||
|
||
|
||
GND
|
||
|
||
|
||
Figure 6
|
||
|
||
|
||
IC1 latches AD1 to AD4 to provide 4 stable address lines during the START and ALE pulse to the
|
||
ADC0816. IC3A combines IOWR and EES to provide a positive going pulse to set the cannel address
|
||
and start a conversion. IC3B combines IORD and EES to provide a positive going pulse to enable the
|
||
digital data onto the ADO-AD7 bus. The clock line from the serial channel SCK is used as a free running
|
||
1.536 MHz clock source, this is divided by 4 by IC2 to provide a 384 KHz clock for the ADC0816. The
|
||
end of conversion signal (EOC) is connected directly to the INTR input to provide an interrupt when the
|
||
conversion is complete.
|
||
|
||
|
||
Example three is a TTL level RS232 expansion device that can be connected to a reduced or extended
|
||
expansion slot. »
|
||
|
||
|
||
Figure 7 shows the schematic of A TTL RS232 based expansion device.
|
||
|
||
|
||
3 THE SIBO EXPANSION PORTS
|
||
|
||
|
||
po RS 400K
|
||
|
||
|
||
. RQ 100K
|
||
pa? pa2———_.D
|
||
ears carat
|
||
mus, Sma,
|
||
|
||
pe RS 106K
|
||
earner se)
|
||
|
||
|
||
GND
|
||
|
||
|
||
vec ai
|
||
PNE
|
||
|
||
|
||
IC2 74HCT244
|
||
|
||
|
||
RITE Ea : : c3+
|
||
EXPANSION : O.1uF per chip
|
||
v ——<EI :
|
||
eee Th. ANPUIS..£
|
||
|
||
|
||
Figure 7
|
||
|
||
|
||
The interface is based around a Psion custom chip known as ASICS, this device is a 44 pin plastic quad
|
||
flat pack device and is available from Psion for custom expansion development. This device converts the
|
||
SIBO serial channel into standard RS232 signals and allows the standard RS232 device driver contained
|
||
in EPOC to be used.
|
||
|
||
|
||
Transistor Q1 provides a switched power rail for any other expansion device. This rail will automatically
|
||
be switched off when the RS232 port is closed. D1 is required to isolate the supply so that the external
|
||
device does not back power the SIBO computer when it enters the standby state. If the additional device
|
||
does not require a supply or only uses a few micro-amps then Q1 and D1 can be omitted, Vcc and the
|
||
supply for the expansion device can be connected directly to Vcc2.
|
||
|
||
|
||
If CMOS level.RS232 signals are required IC1 can be replaced with a 74HC244 device. If inverted sense
|
||
RS232 signals are required IC1 can be replaced with a 74HC241 device.
|
||
|
||
|
||
25
|
||
|
||
|
||
ate
|
||
|
||
|
||
rp
|
||
|
||
|
||
,
|
||
Lie a
|
||
af 5
|
||
2 di Pe
|
||
: ra
|
||
*.
|
||
|
||
|
||
INDEX
|
||
|
||
|
||
ADO-AD7 signal 20
|
||
ALE signal 20
|
||
analog interface 23
|
||
ASIC1 1
|
||
8/16-bit bus 2
|
||
1/0 decoding 4
|
||
interrupts 4
|
||
memory decoding 3
|
||
protected mode 4
|
||
ASIC2 1, 4
|
||
serial protocol 5
|
||
ASIC3 2,9
|
||
power supply 8
|
||
ASIC5 25
|
||
ASICS 1,9
|
||
addressing 6
|
||
buzzer 4
|
||
CODEC 7
|
||
sound interrupt 8
|
||
Control frames 12
|
||
Data input frames 12
|
||
Data output frames 12
|
||
EES signal 20
|
||
|
||
|
||
eight channel controller 11
|
||
expansion connector 22
|
||
|
||
|
||
expansion port 5, 22
|
||
|
||
|
||
extended expansion port 19
|
||
|
||
|
||
Flash 6
|
||
|
||
addressing 7
|
||
FRC 6, 7
|
||
|
||
interrupt 8
|
||
free running clock 22
|
||
|
||
|
||
Free running counter 6, 7
|
||
|
||
|
||
HALT 2
|
||
HC 1
|
||
ASIC1 2
|
||
high speed link 5
|
||
i/o timing 21
|
||
IN instruction 23
|
||
INTR signal 21
|
||
IORD signal 21
|
||
IOWR signal 21
|
||
keyboard 4
|
||
interface 5
|
||
MC 1
|
||
ASIC1 2
|
||
memory pack 11
|
||
Null! frames 12
|
||
OUT instruction 23
|
||
power control!IC 11
|
||
power supply 5
|
||
ASIC2 4
|
||
expansion 22
|
||
HC 8,9
|
||
MC 8,9
|
||
|
||
|
||
Series 3 8,9
|
||
RAM
|
||
addressing 6
|
||
read/write port 23
|
||
reduced expansion port 22
|
||
ROM
|
||
|
||
addressing 6
|
||
|
||
addressing two sites 7
|
||
RS232 interface 24
|
||
serial channel clock 22
|
||
serial transfer rate 11
|
||
Series 3 1
|
||
Series 3a 1
|
||
|
||
ASICS 6
|
||
|
||
expansion support 7
|
||
SIBO Protocol Slave (SPS) devices 14
|
||
SSD 4, 5, 6, 7
|
||
|
||
power supply 9
|
||
SSDs 5
|
||
V30H 1
|
||
|
||
addressing 6
|
||
|
||
ASICS 6
|
||
|
||
speed 6
|
||
|
||
|
||
BC
|
||
|
||
|
||
2 ry
|
||
ig«aa
|
||
4 wee “
|
||
is eye » a «4 . hi
|
||
Sen 1 OP linn (te
|
||
quot
|
||
“a eer «
|
||
ee
|
||
‘ o? yon >
|
||
|
||
|
||
BY reine - mer
|
||
ree ad we «
|
||
athe
|
||
|
||
op @%
|
||
|
||
|
||
= & Mie
|
||
ee he
|
||
S pee) Pye thew.”
|
||
|
||
|
||
P a | -
|
||
‘ ve a Ww
|
||
é
|
||
? r
|
||
i)
|
||
4
|
||
a»
|
||
vy
|
||
|
||
|
||
(a0ul
|
||
|
||
|
||
OS wrr.e Wis cue
|
||
|
||
|
||
etsy * 4
|
||
|
||
VS eceTeS Se) ay
|
||
|
||
° 9 Me é
|
||
% gun «rele
|
||
+ cic thy
|
||
& erate
|
||
|
||
|
||
muhuwd wet
|
||
+ @hSi ole beg
|
||
if tite
|
||
7 tain wd
|
||
Y 7 eae,
|
||
8 Veet ooru
|
||
«
|
||
u,! Cee
|
||
2B: 2) Jes.
|
||
> 1s p
|
||
|
||
|
||
A vine) Some
|
||
r?. were wil
|
||
| Petes? Myer’ ep Q
|
||
y i” @ yi ian nQ
|
||
|
||
|
||
if hw : -—)
|
||
LL 1: vinte wy y
|
||
% j ig ve ' ri
|
||
|
||
[ ? ooh y ontarene
|
||
|
||
|
||
ae | 7ae “new; wr
|
||
|
||
|
||
& wel)
|
||
pvrinewelibie
|
||
(yy Teer
|
||
aw "et 4qea!
|
||
elie em. eas
|
||
& * Ab
|
||
' mi
|
||
|
||
| ica
|
||
40 Ves ® Niet
|
||
grea <)
|
||
“> (er ifr
|
||
‘ia ener
|
||
* APS (aD!
|
||
fs. irq BUC!
|
||
& Wiaerye
|
||
|
||
1 on™. ©
|
||
3M
|
||
|
||
> ¥ HeA
|
||
‘7 B imig i“ ve
|
||
re oper’ upg
|
||
Co Weetye tte! FV
|
||
> twah rw +>
|
||
‘ata hs &
|
||
|
||
|