HARDWARE REFERENCE Version 2.10 NOTE: The data in this manual is provided for information only. You are strongly advised not to make direct access to any of the hardware since this may conflict with access made by EPOC. To guarantee future compatibility, hardware access should only be made via the apropriate operating system calls. February 3, 1995 (C) Copyright Psion PLC 1990-95 All rights reserved. This manual and the programs referred to herein are copyrighted works of Psion PLC, London, England. Reproduction in whole or in part, including utilization in machines capable of reproduction or retrieval, without express written permission of Psion PLC, is prohibited. Reverse engineering is also prohibited. The information in this document is subject to change without notice. Psion and the Psion logo are registered trademarks, and Psion, Psion MC, Psion HC, Psion Series 3, Psion Series 3a and Psion Workabout are trademarks of Psion PLC. IBM, IBM XT and IBM AT are registered trademarks of International Business Machines Corp. Microsoft and MS-DOS are registered trademarks of Microsoft Corporation. Apple and Macintosh are registered trademarks of Apple Computer Inc. VAX and VMS are registered trademarks of Digital Equipment Corporation. 80C86, 8088, 8288, 8259 and SLD are registered trademarks of Intel Corporation. V30 and V30H are registered trademarks of NEC Corporation. Brief is a registered trademark of Underware Inc. Psion PLC acknowledges that some other names referred to are registered trademarks. SE ee a ae es Contents —_— eee T ‘The. Principali Chip Seti. iivediodscesscsen ec ennertete teste teak iotaseveieee hs Beckcecek 1 PRG Ma ixs coe coer er iasares cud cthtenteranadlanss tak peeen aed scdavaei wis APU cos ne CIS al edits 2 BuUSSCONtCONE Rs «sas sewaschsv ae sicnne sescaueenpecy mrs roe Fe Sees set ee ee 2 BUSS CONVENED .0:cs ROWCO-7 9 ROWCO-7) SYSTEM OSCILATOR a Figure 1. HARDWARE REFERENCE A en ree] ASIC1 ASIC1 contains approximately 4300 gates, implemented on a Hitachi one micron CMOS gate array in a 100 pin quad flat pack package. ASIC1 is the main system controller for the SIBO architecture. It connects directly to the 80C86 in maximum mode controlling all bus cycles to and from the processor. This configuration effectively forms a micro-controller like device that executes 8086 instruction codes. ASIC1 is made up of a number of functional blocks described below. The bus controller converts the encoded bus cycle requests (present on SO-S2) from the processor into the appropriate memory and I/O control signals. The bus controller is similar to the Intel 8288 device but with several enhancements, these are:- 1) Clock stopping on the HALT instruction. Whenever a HALT instruction is issued by the processor the clock line to the processor is stopped and held low until either an NMI or an interrupt is asserted. 2) Bus arbitration during video refresh cycles. Bus cycles to the video RAM segment are delayed while a video refresh is in progress. 3) Memory write and I/O blocking. Memory writes outside pre-programmed segments and all 1/O instructions can be blocked by the bus controller. See following sections on address and 1/O protection. Memory access to the 8-bit bus are converted to 16 bit accesses by the bus converter. This means that the 80C86 can access memory on the 8-bit bus as if it were 16-bits wide. ASICI can operate in two modes dependant on a strapping pin: 16 bit memory mode or 8 bit memory mode. 16 bit mode allows higher processor clock speeds for a given memory access time but requires a full 16 bit bus and hence 16 bit wide memory. 8 bit mode requires higher speed memory for a given processor clock speed but only requires an 8 bit bus and 8 bit wide memory. In all MC's ASIC] operates in 16 bit mode, while the HC operates in 8 bit mode. In 16 bit mode all the system memory except for the video RAM is connected to the 16 bit bus. The video RAM is defined as a 32K segment of RAM between B8000 and C0000 hex. Any memory access to this segment is converted to two 8 bit memory accesses on the 8 bit bus by the bus conversion logic. These accesses may delay the 80C86 by stopping the clock to allow time for the two accesses or to allow a video refresh access to take place. In 8 bit mode all system memory is connected to the 8 bit bus so all memory accesses need to be converted. This means that memory needs to be faster for a given clock speed than in 16 bit mode, because two memory accesses need to be "squeezed" into one bus cycle. The video RAM is just part of the system RAM and is of variable size dependent on the LCD screen size with a base address of 400 hex. Timer A general 16 bit count down timer is provided by ASIC]. When the system is not in the standby state i.e. the processor is running, the clock source can be programmed to be either a fast (512 KHZ) clock or a slow (32 Hz) clock. Any 16 bit value can be written into the timer at any time. This value will then be decremented on the next rising edge of the clock. The current value in the timer can be read at any time. When the value in the timer reaches zero an interrupt is generated. When the system is in the standby state the timer is clocked from the 32 Hz real time clock oscillator in AS/C3 so that time can be kept while the processor is powered down. The timer can operate in two modes controlled by a programmable bit, free running mode or prescale mode. In free running mode, when the timer decrements to zero an interrupt is generated and the counter just wraps around to -1 (FFFF). In prescale mode when the interrupt is generated the original value written to the timer is re-loaded automatically, this allows the interrupt to become a rate programmable pulse stream. This pulse stream is also an output from ASICI. 1 THE PRINCIPAL CHIP SET The LCD controller provides all the necessary ti of up to 640 by 400 dots in size. The data is output on up to eight signals. Each data signal outputs serial data that is synchronous with the dot clock. The data is a continuous bit stream formed from serialised data taken from the video refresh RAM. The data is serialised so that the first pixel in a line is bit 0 in the corresponding byte of the video RAM, this means the video RAM can be accessed in words i.e 16 bits wide. The timing and data signals are controlled by a number of programmable registers which allow the following parameters to be set: 1) Lime length - the number of dots in the line. 2) Frame length - the total number of dots in the screen. 3) Refresh rate - sets the refresh rate. This should be calculated from the system clock speed and the screen size to give a refresh rate of approximately 70 frames per second. 4) AC drive rate - sets the frequency of the AC drive signal to the LCD module as a function of the line rate. This should be calculated to be approximately 300 Hz. 5) Display mode - four different display modes are supported these are: single screen refreshed from video page one; single screen refreshed from video page two; single screen refreshed from video page one and two giving a two bit grey scale; and double screen refreshed from video page one and two. 8 bit memory decoding allows for different sized physical memory devices to be connected to the logical memory slots. Three memory device size options are supported allowing for 32K x 8, 128K x 8 and 512K x 8 devices to be addressed. These options are selected by two programmable bits, MSELO and MSELI. The following table summarises the memory device size options:- MSEL1 MSELO Device size The following table summarises the memory decoding performed by ASICI:- 00000 - IFFFF 8 Bit slot 0 00000 - O7FFF 00000 - 7FFFF 8 Bit slot 1 08000 - OFFFF | 20000 - 3FFFF 80000 - FFFFF 8 Bit slot 2 10000 - 17FFF | 40000 - SFFFF - 8 Bit slot 3 18000 - 1FFFF | 60000 - 7FFFF - 8 Bit slot 4 20000 - BFFFF | 80000 - BFFFF 80000 - BFFFF 8 Bit slot 5 C0000 - FFFFF} C0000 - FFFFF C0000 - FFFFF B8000 - BFFFF 00000 - B7FFF + C0000 - FFFFF 16 Bit 8 Bit slot 1 16 Bit 16 Bit slot HARDWARE REFERENCE 0300 - FFFF Not used 0200 - 02FF Expansion port 2 0100 - O1FF Expansion port 1 0090 - OOFF Not used 0080 - 008F I/O space in ASIC2 0020 - 007F Not used 0000 - 001F Internal I/O in ASICI The interrupt controller in AS/CJ prioritises eight interrupt request lines to generate a single interrupt request to the processor. When and if the processor executes an interrupt acknowledge cycle, the interrupt controller places the correct vector on the bus. The interrupt controller is similar to the Intel 8259 device, however, the following restrictions apply; there is no provision for daisy-chaining additional interrupt controllers, level triggered mode only is supported and the interrupt vector base is fixed at 78 hex. The 8 interrupts are defined internally in ASJCI as follows: 78 Tick interrupt at 2 or 32 Hz External interrupt usually connected to mains detect bit External interrupt from expansion port one External interrupt from expansion port two External interrupt from ASIC2 SLD sound receive interrupt SLD sound transmit interrupt Watchdog timer —S<—h 3 vhUhm™m™C™t~—O—OCOCC—O The watch dog timer is a two bit counter which counts up at a rate of 4 Hz. If the count reaches three a NMI is generated. The counter can be reset by a write to an I/O location inside ASJC1. Normally the counter is reset on every tick by the interrupt service routine. The NMI will be produced after 24 ticks have passed with no reset, this equates to 0.75 of a second with interrupts disabled. The range is set by writing the upper and a lower segment bounds for the given range to two internal 16 bit registers in ASIC]. Protected mode is switched on and off by writing to or reading from a special I/O location in ASICI. eA ASIC2 ASIC2 contains approximately 2200 gates, implemented on a Hitachi one micron CMOS gate array in an 80-pin quad flat pack package. ASIC2 contains the system clock oscillator, controls switching between the standby and operating states, and provides an interface to the power supply, keyboard, buzzer, SSDs and expansion ports. ASIC2 consists of the following functional blocks: 1 THE PRINCIPAL CHIP SET ee EEEeEEEFSFSFSSSSSSSSSSSSSSSSSSMMsFsFeFesesesesesMsSSSFSsFsFse An on-chip oscillator cell connected to an external crystal generates the main system clock in the operating state. The system clock frequency is divided down to provide clocks for the serial channels, the SLD bus interface and for RS232 communication. The oscillator is disabled in the standby and battery backup states to conserve power. ASIC2 controls switching between the standby and operating states. AS/C2 puts the system into the operating state when: the keyboard "on" signal is asserted; the system "reset" signal is generated; an expansion device requests service; an external controller initiates a "high speed link" or the AS/C/ timer reaches zero. Switching from the operating state to the standby state is software controlled. When an "enter standby" command is written to ASIC2 it shuts down the power supply via the serial interface and puts the system into the standby state. ASIC2 contains an 8-channel SIBO serial protocol controller which provides an interface to the power supply, the SSDs, the expansion ports and the high speed link. Channel assignments are: Power supply (ASIC3) SSDs Expansion ports High speed link Serial clocks 5 & 6 may be set free running at 1.536Mhz, this frequency may be divided down by devices connected to the expansion ports to provide baud rates for RS232 communication. To maximise the data transfer rate, a "controller busy" signal is generated by ASIC2 during a data transfer. This signal is connected to the processor TEST pin. For further details refer to "The SIBO serial protocol” chapter of this manual. is used for the "high speed link" to receive data transmitted by an external controller. An interrupt is generated when a frame is received. ASIC2 provides an interface to a matrix keyboard of up to 192 keys, made up from 16 rows by 12 columns. During a keyboard scan the columns are each driven high in tum by ASIC2 and the row information is read from the keyboard row register. Normally the row buffer is 8 bits wide which gives a matrix of 8 x 12 i.e. 96 keys. A piezo electric buzzer element can be connected directly to AS/C2. The buzzer can be driven at high or low volume, and either directly by toggling an ASIC2 register bit or by the overflow bit from the ASIC! timer. NMI g ASIC2 controls the generation of an NMI which is passed onto the processor via ASIC. This NMI can be generated from a number of sources, these are, power fail conditions and SSD or expansion port door micro-switches. When the main power supply voltage (Vsup) falls to a level insufficient to power the system ASIC3 signals ASIC2 and a power fail NMI is generated. When an expansion device is removed or inserted, or if an SSD is removed or inserted micro-switches connected to ASIC2 generate the appropriate NMI. The source of the NMI is identified by reading a register in ASIC2. HARDWARE REFERENCE SS SSS ee ee | ASICS The Series 3a differs from the above description in that the V30H and all the functions in ASIC] and ASIC2 have been integrated into a single custom device known as ASIC9. This has allowed faster processing speeds and lower power consumption to be achieved. In addition a number of enhancements and alterations have been made to the SIBO architecture listed below. . This allows larger mas ROM's and RAM's to be addressed. This is done by implementing bank switching in ASIC9 which will be similar to EMS on PC's. Each bank is 64 KBytes in size and is selected by writing into one of four page registers, two to select a RAM address and two to select ROM addresses. These page registers are called PSELO to PSEL3 respectfully. This method extends the V30H address capability by 4 bits to produce two 24 bit address bus ranges, one for RAM and one for ROM. This gives an affected linear address range of 32 MBytes. The 16 MByte RAM space is decoded into 4 Chip selects allowing up to 8 x 16 Mbit RAM devices (2 per chip select as 16 bit wide). The 16 MByte ROM space is decoded into two chip selects each selecting 8 MBytes each, one for mask ROM and one for FLASH memory. The physical address map for the V30H now looks like this:- 00000 - SFFFF | Maps to physical bottom 384K of the 16 Mbyte RAM space. 60000 - 6FFFF | Maps to 64K RAM segment selected by page register PSELO. 70000 - 7FFFF | Maps to 64K RAM segment selected by page register PSEL1. 80000 - 8FFFF | Maps to 64K ROM segment selected by page register PSEL2. 90000 - 9FFFF | Maps to 64K ROM segment selected by page register PSEL3. A0000 - FFFFF | Maps to physical top 384K of the 16 Mbyte ROM space. = Se Although the V30H microprocessor is rated at clock speeds of up to 16 MHz, the Series 3 machine is currently limited to a clock speed of 3.84 MHz. This is due to the fact that ASICi accesses the ROM as two 8 bit bytes to assemble a 16 bit word for the V30H. This equates to a required ROM access speed of approximately 250 nSec for a 3.84 MHz clock. Readily available mask ROM's have an access speed of 200 nSec which currently limits the clock speed of Series 3. ASIC9 supports 16 bit wide accesses to memory space which allows a doubling of the clock speed for the same ROM access time. In addition ASIC9 will support programmable wait states so that faster clock speeds can be used with slow ROM's or RAM's. more closely to the bus controller. This is now possible as they are both in the same chip. The serial controller can now automatically hold the processor (by stopping the CPU clock) if it attempts to issue a command to the controller whilst it is busy. This reduces to zero the overhead involved in determining this condition. This technique should also enhance the speed that Flash memory devices can be written to. Addition of hardware 32 b =—séC The ASICI/ASIC2 implementation of the SIBO architecture uses the FRC (Free running counter) to maintain time while the CPU is powered down (in standby). This means the CPU must wake up at a periodic rate (approx 8 hours) to keep time, if the CPU cannot start (no main batteries) time is lost. To overcome this limitation AS/C9 contains a separate 32 bit real time clock that will continually maintain the system time independently from the CPU. This counter will be clocked at 1 Hz so its maximum range will be 232 seconds or approx 136 years. 1 THE PRINCIPAL CHIP SET EEE ASIC9 contains a 16 FIFO buffer to reduce the CPU overhead involved in playing or recording sounds via the CODEC device. ASIC9 contains the logic to bring the system out of the standby state if any of a set number of row inputs goes high. This allows Switch on via the membrane key pads. The 16 MByte paged ROM address will be split into twe sections each 8 MBytes in size. It is intended that one section is for mask ROM one for FLASH memory. ASIC9 contains an additional FRC (Free Running Counter). This FRC is functionally identical to the current FRC but is indented for general user use and is not used by EPOC. This second FRC can be clocked from either 512 KHz or 1024 Hz. This extends the use of the FRC by providing a counter with a resolution of 1 mSec and a range of just over one minute. This could help software time events in the mSec range i.e. a stopwatch. The mapping of the two video maps has been improved to reduce the overhead that grey scales impose on software. This improved scheme supports only one grey level together with black and white. The second video map is an attribute map and would have the effect of dimming only those pixels that are set i.e. black. “ ASIC9 contains three serial control registers and three read data registers. This allows independent expansion devices to be added to either SSD slot. The main advantage of triple registers is that a multiple-mode pack read can be interrupted at anytime by a read or write to any of the other serial channels without loss of setup and data, for example servicing an RS232 interrupt from either SSD slot. The ASICI/ASIC2 implementation of the SIBO architecture positions the two video maps so that they are separated by a fixed address space (16K 4000H). This restriction is overcome in ASIC9 by Starting the second video map directly after the first video map regardless of the size of the video maps. in SS Two active low external interrupt inputs are provided by ASJC9 which can be connected to the VBACK outputs on two SSD sockets. This will allow SSD sized expansion devices to be fitted internally to the Series 3a. The Interrupt allocation has been changed in AS/C9 so that sound processing is serviced at the highest priority. Interrupts are allocated as follows:- CSINT CODEC sound interrupt. TINT 32 Hz tick interrupt. SSINT Serial slave interrupt. EINTO External interrupt input 0. EINT1 External interrupt input 1 (inverted). EINT2 External interrupt input 2 (inverted). FRC1OI FRC1 overflow interrupt . FRC20I1 FRC2 overflow interrupt. PSU subsystem SIBO architecture power supplies all differ depending on the system requirements. MC and HC power supplies have higher current ratings to support a wide variety of expansion devices and are based around 7.2 volt NiCd batteries. The Series 3 and its derivatives have a lower current rating and are based around two 1.5 volt alkaline batteries. MC and HC power supplies are based on a full custom liner ASIC known as ASIC3. This custom chip is manufactured by Maxim and has the Maxim part number MAX616. The power supply provides a number of switched power rails from one unregulated supply rail known as Vsup. This supply is typically connected to the main battery in the system and can be in the range 5.5 to 12 volts. These supply rails are derived from Vsup from either PNP pass transistor linear regulators or from switch mode regulators. Series 3 power supplies generate a sub-set of the rails listed below from a number of switch mode regulators. SIBO architecture power supplies all operate in four principal states, these are; standby, backup idle and operating. Th : 2 In the standby state the main oscillator and the processor are shut down. ASICI, ASIC2 and the memory are powered and the real time oscillator is running to keep time. The timer in ASJCI is used in this mode to keep time while the processor is powered down. All other supply rails are switched of in this state. The backup state only exists when the main battery supply has failed or is not present. State is the same as the standby state except that Vccl is now powered from the backup battery input and switching to the operating state is inhibited. In the idle state the processor is powered up and the main system oscillator is running: the switchable supply rails may be on depending on software instructions. The processor clock is stopped and the processor is idle and waiting for an event i.e. an interrupt. This means that the bus is not active apart from LCD screen refresh accesses. ating state __—sdiziéts =—i—0 Reset specific slave with ID = xx 0 1 0 Deselect slave (does not reset slave) 0 1 xx< >0 Select slave with ID=xx and read slave info (see below). The Reset function is dependant on the slave. It would normally put the slave into a known passive reset State. Select Slave with ID=xx (S=0,R=1) This is a special command that causes a slave with ID=xx to transmit to the controller an 8 bit information field. This field depends entirely on the slave but must be non zero. A reply of 0 indicates that there is no slave of the requested ID present. command described above. The format of the control word in slave select mode is as follows: Key R/W Read/write select. 0 = write, 1 = read B/W Data transfer size. 0 = 1 byte transfer, 1 = word (2 byte transfer). S/M Single/Multi transfer mode. 0 = single, 1 = multibyte. XXXX 4 bits of data to slave. Note the meaning of the 4 bits of data (XXXX) is entirely dependent on the slave. The settings of R/W,B/W,S/M bits in the control word determine the size, type and direction of subsequent data transfers in the following manner: 15 HARDWARE REFERENCE —_— gs eeeSSSEeeeSSSSSSSSFSSSSSMSSN 2 2 S/M write a single byte to slave write a number of single bytes to slave write a byte pair to slave write a number of byte pairs to slave read a number of single bytes from slave read a byte pair from slave = SY —& -&§ CO FO OC OO 0 1 0 1 0 read a single byte from slave 1 0 1 - Fe OF 0O KF &§ CO 0 read a number of byte pairs from slave Write a single byte This command readies the currently selected slave to receive a byte of data and sets up the controller so that the next byte (or the LSB of a word) written to its data register will be transmitted to that slave. Anything further written to the controller's data register will have no effect. Write a number of single bytes This command readies the currently selected slave to receive a number of sequential bytes of data. The slave will expect to receive data bytes until another control byte is received. The controller is set up so that the next byte (or the LSB of a word) written to its data register will be transmitted to that slave. All subsequent bytes written to the controller's data register will be transmitted to the slave. This will continue until another byte is written to the controller's control register. Write a byte pair This command readies the currently selected slave to receive two bytes of data and sets up the controller so that the next word written to its data register will be transmitted to that slave (LSB first). Anything further written to the controller's data register will have no effect. Write a number of byte pairs This command readies the currently selected slave to receive a number of sequential byte pairs of data. The slave will expect to receive byte pairs until another control byte is received. The controller is set up so that the next word written to its data register will be transmitted to that slave (LSB first). All subsequent words written to the controller's data register will be transmitted to the slave. This will continue until another byte is written to the controller's control register. Read a single byte This command triggers a byte to be transmitted from the selected slave to the controller. This byte can then be read from the LSB of the controller's data register. Further reads of the controller's data register will return the same data but have no effect on the protocol. Read a number of single bytes This command triggers a byte to be transmitted from the selected slave to the controller. This byte can then be read from the LSB of the data register. This read will trigger the next byte to be transmitted to the data register of the controller. All subsequent reads of the controller's data register will trigger further bytes to be transmitted to the controller. This will continue until another byte is written to the controller's control register. Read a byte pair This command triggers a byte pair to be transmitted from the selected slave to the controller. This word can then be read from the controller's data register. Further reads of the controller's data register will return the same data but have no effect on the protocol. Read a number of byte pairs This command triggers a byte pair to be transmitted from the selected slave to the controller. This word can then be read from the controller's data register. This read will trigger the next byte pair to be transmitted to the data register of the controller. All subsequent reads of the controller's data register will trigger further byte pairs to be transmitted to the controller. This will continue until another byte is written to the controller's control register. 16 2 THE SIBO SERIAL PROTOCOL wn below. The time is given in SIBO pack protocol clock cycles. The length of a clock cycle is nominally 260 nanoseconds for a clock frequency of 3.84 MHz. Receive and process the control byte 12 cycles Byte transfer to or from slave 12 cycles Byte pair transfer to or from slave 24 cycles When writing to the controller's data and control registers the following rules apply:- 1) After writing to the control register there must be a delay of at least 12 cycles before the data register is accessed or another control word is written. 2) To read a word from the data register after the command to read byte pair is issued there must a delay of at least 12 (for control byte) + 24 (for the byte pair transfer) = 36 cycles. 3) To perform a multiple byte pair write there must be a delay of at least 12 cycles after the command is written to the control register before the first word can be written to the data register and a delay of at least 24 cycles between subsequent writes to the data register. A slave can be in one of 5 states. Note a control byte can be received and interpreted at any time. 1) Waiting to receive a data byte or control byte 2) Waiting to receive a data byte pair or control byte 3) Waiting to transmit a data byte or control byte 4) Waiting to transmit a data byte pair or control byte 5) Waiting to receive control byte only The following table shows the state after each control word is received S R Dow Slave select 0 0 0 Reset all 0 0 <>0 Reset slave | 0 Deselect slave Oo 1 <>0 Select slave S RW B2B SM XXXx 1 0 0 0 x write byte 1 OQ 0 1 x write bytes 1 0 1 0 x write byte pair 1 0O 1 1 x write byte pairs 1 1 0 0 x read byte 1 1 0 1 x read bytes 1 1 1 0 x read byte pair 1 1 1 1 x read byte pairs 17 CHAPTER 3 THE SIBO EXPANSION PorTS The SIBO architecture allows for two types of expansion device, extended internal expansion and reduced external expansion. Extended internal expansion slots provide direct I/O with the processor, a SIBO serial channel, and connection to the power supply. It allows for higher powered expansion devices to be added by including a direct connection to the main 7.2 volt battery. The MC and HC products both support two independent extended internal expansion slots. Reduced external expansion is based on a single SIBO serial channel only and has very limited power available ( < 25 mA ). The Series 3 and 3a supports a single reduced external expansion slot only. ———E SSS eee ee ee eee Extended internal expansion 98148-1182 EXPANSION DEVICE COMPONENT SIDE 99148-1123 SIBO COMPUTER Figure 2 The 26th position is a polarising key and should be left blank. The correct mating connector on the expansion device is made up from a number of Molex C-Grid series 90148 connectors. Pins 1 and 2 are 19 HARDWARE REFERENCE GND and should have there own connector placed nearer the board edge to ensure the GND connection is made first when the expansion device is inserted. The required connectors are Molex 90148-1102 for the GND contacts and Molex 90148-1123 for the signal contacts. Should mate first when device inserted Should mate first when device inserted B CMOS] 8 bit multiplexed address and data bus pulled low with 100 K resistors B CMOS O CMOS} I/O write strobe - active high, data valid on falling edge of IOWR O CMOS] I/O read strobe - high when device can place valid data on ADO-AD7 O CMOS| External Expansion Select - high during I/O cycles to expansion device Reserved Reserved Reserved Used to enable reprograming of internal system Flash memory Unregulated battery voltage - present all the time I CMOS | Active high interrupt input I CMOS | Active low input pulled up to Vcci - pull low to switch machine on B CMOS| SIBO serial protocol data line - pulled low T CMOS| SIBO serial protocol clock line - Hi-Z in standby needs a pull down Power Power | +5 volt supply, switched off in standby. Max current available = 50 mA The signal types are: O CMOS CMOS output to the expansion device. B CMOS CMOS bi-directional line to the expansion device. T CMOS CMOS tri-state output to the expansion device. 1 CMOS CMOS input from the expansion device. All the CMOS signals including the ADO-AD7 bus are buffered from the main system busses and so present a load of one HC series logic gate. Expansion devices can be connected to direct processor I/O space using the following signals; ADO-AD7, ALE, IOWR, IORD, EES and INTR. ADO-AD7 is the least significant half of the multiplexed address and data bus, this means that up to 128 I/O addresses are available for each expansion device. As only the least significant half of the bus is available and no bus conversion is done only even addresses can be used. ALE must be used to latch the address from ADO-AD7 for devices that require a stable address. The address is valid on the falling edge of ALE. Note that AO will always be low for valid writes to the expansion device and as such should not be used as an address line, Al should be used as the lowest order address line. AO can be used as an additional enable signal to stop odd I/O accesses disturbing the expansion device (see example 1). EES is the External Expansion Select and is high during all I/O accesses to the expansion device, i.e. for I/O reads and writes to address range 100 to 1FF hex. for expansion port 1, and 200 to 2FF for expansion port 2. 20 3 THE SIBO EXPANSION PORTS IOWR is an active high signal which is high during all I/O write bus cycles. The data on ADO-AD7 is guaranteed to be stable before the rising edge of IOWR and after the falling edge of IOWR. IORD is an active high signal which is high during all I/O read bus cycles. The ADO-AD7 bus is guaranteed to be tri-state before the rising edge of IORD and after the falling edge of IORD. The expansion device must present valid data on the bus when IORD is high, see the timing details below. INTR is an active high interrupt input to ASJC1. This can be used as a directly readable bit or as a dedicated interrupt input. It must not be driven high when the system is in the standby state as this input is pulled down and will cause excessive standby current consumption. Figure 3 shows the timing of the I/O write and read cycles. 1/0 WRITE CYCLE : : /VVV , ADB-AD7 VALID _ADDRX X XXX VALID WRITE DATA : ALE Fes ALE EES IORD Address set up time Address hold time Write data set up time Write cycle pulse width Write data hold time Time from Hi-Z to data active Read cycle pulse width Read data set up time Read data hold time Note the typical values given are for an MC with a system oscillator of 15.36 MHz, the HC times will be approximately twice as long. The minimum times given are for projected higher speed MC devices with oscillator frequencies of up to 23.04 MHz. 21 HARDWARE REFERENCE a kw eS 1.536 MHz regardless of the system clock frequency. This frequency is a multiple of the SLD clock rate and of all normal RS232 baud rates. Two power supplies are available for expansion devices these are Vcc2 and Vsup. Vec2 is a +5 volt supply that is derived from Vsup. Vec2 is switched off when the system is in the standby state and is switched on when the operating or idle state is entered. Each expansion device can draw up to 50 mA from Vcc2. If an expansion device requires more than 50 mA or cannot be powered down when the system is in the standby state the Vsup power supply must be used. Vsup is the unregulated supply directly from the main system batteries or from the DC jack input. It will be in the range 5.5 to 12 volts under normal conditions. To use Vsup the expansion device must regulate Vsup to 5 volts with a low drop-out linear regulator. Care must be taken to not be active and driving any signals high when the system is in the standby state as Vsup is always present. This can be achieved either in software or by using Vcc2 as a signal indicating the active state. SSE, EE ee ae ee eee Reduced external expansion The reduced expansion port is made up of a 6 way two row connector spaced on a 2 x 3 way 0.1 inch pitch. Figure 4 shows the physical connector numbering. Looking into Series 3 / 3a Figure 4 MSD Master SIBO serial protocol data line - pulled low MCLK Master SIBO serial protocol clock line - low in standby Vec +5 volt supply, switched off in standby. Limited to 25 mA GND Signal ground, this signal should mate first when connector inserted SSD/INT Slave SIBO serial data line or active high interrupt input Slave SIBO serial clock line or active high switch on input MSD and MCLK form a single master SIBO serial protocol channel, this is normally channel 7. The serial channel clock can be continuously enabled to provide a free running clock for expansion devices. The frequency is fixed at 1.536 MHz regardless of the system clock frequency. SDS/INT and SCK/EXON are both dual function pins. SDS and SCK form a single slave SIBO serial protocol channel, this can be combined with MSD and MCLK to form a bidirectional high speed data link. SDS/INT can also be used as an active high interrupt input. The function of SDS/INT can be programmed in ASIC2 or ASIC9. A rising edge on the SCK/EXON input will bring the system out of the Standby state into the operating state. VCC is a +5 volt supply that is switched off when the system is in the standby state and 22 3 THE SIBO EXPANSION PORTS is switched on when the system is in the operating or idle state. The maximum current that can be drawn is 25 mA. ha Se ee ee eS ee a el Example expansion devices Two examples are given to illustrate using the direct I/O expansion signals present in an extended SIBO expansion port. A further example is given using a SIBO serial channel for both reduced and extended expansion slots. ExaER one is a ‘ile 8 bit read/write port. 8 LEDs can be set ie an OUT instruction and the state of an 8 bit DIL switch can be read by an IN instruction. Figure 5 shows the schematic of such a port. = Eee te a tae a [ia] =I a [ae vs iis 4 274 2ag Le) 2 16p Bch ai ji 26) IT 8x100K GND GNO GND GND GND GND GND GNO 8 x Lav current LEOs cs LOOnF Figure 5 Note that the port is powered from Vcc2 which has a maximum current budget of 50 mA so low current LEDs must be used. IC3B latches the state of ADO to provide a stable AO line, this is used as an additional enable signal, so that only even I/O cycles will effect the state of the port. IC2A combines AO, EES and IORD to provide a negative going pulse during any even read to the expansion port address range. IC2B combines AO, EES and IOWR to provide a negative going pulse during any even writes to the expansion port address range. IC2C just inverts the sense of ALE so that address can be latched on the rising edge by IC3B. wo - 16 channel ADC | Example two is a 16 channel analog input interface. It is based on the National Semiconductor part ADC0816. The interface is arranged so that a write to the expansion port address range will start a conversion and select the required analog channel to read. The interrupt input (INTR) is connected to the EOC signal to generate an interrupt when the conversion is complete. Figure '6 ‘shows the schematic of the 16 channel analog interface. 23 HARDWARE REFERENCE MC/HC EXPANSION PORT i cL c2 i c3 ca cs — 6V3 100nF L100nF 406nF 100nF GND Figure 6 IC1 latches AD1 to AD4 to provide 4 stable address lines during the START and ALE pulse to the ADC0816. IC3A combines IOWR and EES to provide a positive going pulse to set the cannel address and start a conversion. IC3B combines IORD and EES to provide a positive going pulse to enable the digital data onto the ADO-AD7 bus. The clock line from the serial channel SCK is used as a free running 1.536 MHz clock source, this is divided by 4 by IC2 to provide a 384 KHz clock for the ADC0816. The end of conversion signal (EOC) is connected directly to the INTR input to provide an interrupt when the conversion is complete. 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