feat: final v1 case design
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@@ -1,8 +1,8 @@
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esp32_width = 25.6;
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case_height = 6;
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esp32_length = 65.5;
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esp32_secondary_length = 60;
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wall_thickness = 0.5;
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esp32_width = 25.8;
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case_height = 12;
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esp32_length = 65.8;
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esp32_secondary_length = 60.2;
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wall_thickness = 1;
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usb_thickness = 3.3;
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usb_width = 9.1;
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@@ -18,21 +18,25 @@ module generateCase() {
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translate([wall_thickness+3,wall_thickness,wall_thickness+1])
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cube([esp32_width-6, esp32_length, case_height]);
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// Generate slot for OTG Port
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translate([wall_thickness+2,0,wall_thickness+1.1])
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translate([wall_thickness+2.1,0,wall_thickness+1.1])
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cube([usb_width,2,usb_thickness]);
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// Generate slot for UART port
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translate([(wall_thickness+esp32_width-usb_width-2),0,wall_thickness+1.1])
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translate([(wall_thickness+esp32_width-usb_width-2.1),0,wall_thickness+1.1])
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cube([usb_width,2,usb_thickness]);
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}
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}
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// 19.5 bracket slot
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module generateBracket() {
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cube(19.5, 10, 0.5);
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module generateLid() {
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union() {
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cube([(esp32_width+(wall_thickness*2)), (esp32_length+(wall_thickness*2)), 1.5]);
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translate([wall_thickness, wall_thickness, 1.5])
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cube([esp32_width, esp32_secondary_length, 1.0]);
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translate([wall_thickness+3, esp32_secondary_length, 1.0])
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cube([esp32_width-6, 5.5, 1.5]);
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}
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}
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generateCase();
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translate([esp32_width+5,0,0])
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generateLid();
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